opt_mem: Remove write ports with const-0 EN.

Fixes #2765.

tests/opt/bug2765.ys

@@ -0,0 +1,34 @@
+read_verilog << EOT
+
+module top(...);
+
+input clk;
+input [3:0] wa;
+input [15:0] wd;
+input [3:0] ra;
+output [15:0] rd;
+
+reg [15:0] mem[0:15];
+
+integer i;
+reg x;
+
+always @(posedge clk) begin
+        for (i = 0; i < 2; i = i + 1) begin
+                x = i == 1;
+                if (x)
+                        mem[wa] <= wd;
+        end
+end
+
+assign rd = mem[ra];
+
+endmodule
+
+EOT
+
+proc
+opt
+select -assert-count 2 t:$memwr
+opt_mem
+select -assert-count 1 t:$memwr