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xilinx: Add xilinx_dffopt pass (#1557)

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Marcin Kościelnicki 2019-12-18 13:42:26 +01:00
parent aff6ad1ce0
commit a235250403
11 changed files with 638 additions and 27 deletions
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2
techlibs/xilinx/cells_xtra.py
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@ -66,7 +66,7 @@ CELLS = [
# CLB -- registers/latches.
# Virtex 1/2/4/5, Spartan 3.
Cell('FDCPE', port_attrs={'C': ['clkbuf_sink']}),
Cell('FDRSE', port_attrs={'C': ['clkbuf_sink']}),
# Cell('FDRSE', port_attrs={'C': ['clkbuf_sink']}),
Cell('LDCPE', port_attrs={'C': ['clkbuf_sink']}),
# Virtex 6, Spartan 6, Series 7, Ultrascale.
# Cell('FDCE'),