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SigSpec refactoring: renamed chunks and width to __chunks and __width

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This commit is contained in:
Clifford Wolf 2014-07-22 19:56:17 +02:00
parent 3b5f4ff39c
commit a233762a81
62 changed files with 954 additions and 951 deletions
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24
passes/techmap/extract.cc
View file

@ -133,8 +133,8 @@ namespace
needleSig.expand();
haystackSig.expand();
for (int i = 0; i < std::min(needleSig.width, haystackSig.width); i++) {
RTLIL::Wire *needleWire = needleSig.chunks.at(i).wire, *haystackWire = haystackSig.chunks.at(i).wire;
for (int i = 0; i < std::min(needleSig.__width, haystackSig.__width); i++) {
RTLIL::Wire *needleWire = needleSig.__chunks.at(i).wire, *haystackWire = haystackSig.__chunks.at(i).wire;
if (needleWire != lastNeedleWire || haystackWire != lastHaystackWire)
if (!compareAttributes(wire_attr, needleWire ? needleWire->attributes : emptyAttr, haystackWire ? haystackWire->attributes : emptyAttr))
return false;
@ -193,7 +193,7 @@ namespace
RTLIL::SigSpec conn_sig = conn.second;
sigmap.apply(conn_sig);
conn_sig.expand();
for (auto &chunk : conn_sig.chunks)
for (auto &chunk : conn_sig.__chunks)
if (chunk.wire != NULL)
sig_use_count[std::pair<RTLIL::Wire*, int>(chunk.wire, chunk.offset)]++;
}
@ -213,7 +213,7 @@ namespace
for (auto &conn : cell->connections)
{
graph.createPort(cell->name, conn.first, conn.second.width);
graph.createPort(cell->name, conn.first, conn.second.__width);
if (split && split->count(std::pair<RTLIL::IdString, RTLIL::IdString>(cell->type, conn.first)) > 0)
continue;
@ -222,9 +222,9 @@ namespace
sigmap.apply(conn_sig);
conn_sig.expand();
for (size_t i = 0; i < conn_sig.chunks.size(); i++)
for (size_t i = 0; i < conn_sig.__chunks.size(); i++)
{
auto &chunk = conn_sig.chunks[i];
auto &chunk = conn_sig.__chunks[i];
assert(chunk.width == 1);
if (chunk.wire == NULL) {
@ -269,7 +269,7 @@ namespace
sigmap.apply(conn_sig);
conn_sig.expand();
for (auto &chunk : conn_sig.chunks)
for (auto &chunk : conn_sig.__chunks)
if (sig_bit_ref.count(chunk) != 0) {
bit_ref_t &bit_ref = sig_bit_ref[chunk];
graph.markExtern(bit_ref.cell, bit_ref.port, bit_ref.bit);
@ -287,7 +287,7 @@ namespace
sigmap.apply(conn_sig);
conn_sig.expand();
for (auto &chunk : conn_sig.chunks)
for (auto &chunk : conn_sig.__chunks)
if (sig_bit_ref.count(chunk) != 0) {
bit_ref_t &bit_ref = sig_bit_ref[chunk];
graph.markExtern(bit_ref.cell, bit_ref.port, bit_ref.bit);
@ -334,8 +334,8 @@ namespace
RTLIL::SigSpec sig = sigmap(conn.second);
if (mapping.portMapping.count(conn.first) > 0 && sig2port.has(sigmap(sig))) {
sig.expand();
for (int i = 0; i < sig.width; i++)
for (auto &port : sig2port.find(sig.chunks[i])) {
for (int i = 0; i < sig.__width; i++)
for (auto &port : sig2port.find(sig.__chunks[i])) {
RTLIL::SigSpec bitsig = haystack_cell->connections.at(mapping.portMapping[conn.first]).extract(i, 1);
cell->connections.at(port.first).replace(port.second, bitsig);
}
@ -729,7 +729,7 @@ struct ExtractPass : public Pass {
for (auto cell : cells)
for (auto &conn : cell->connections) {
RTLIL::SigSpec sig = sigmap(conn.second);
for (auto &chunk : sig.chunks)
for (auto &chunk : sig.__chunks)
if (chunk.wire != NULL)
wires.insert(chunk.wire);
}
@ -756,7 +756,7 @@ struct ExtractPass : public Pass {
newCell->parameters = cell->parameters;
for (auto &conn : cell->connections) {
RTLIL::SigSpec sig = sigmap(conn.second);
for (auto &chunk : sig.chunks)
for (auto &chunk : sig.__chunks)
if (chunk.wire != NULL)
chunk.wire = newMod->wires.at(chunk.wire->name);
newCell->connections[conn.first] = sig;

2
passes/techmap/hilomap.cc
View file

@ -31,7 +31,7 @@ static RTLIL::SigChunk last_hi, last_lo;
void hilomap_worker(RTLIL::SigSpec &sig)
{
sig.expand();
for (auto &c : sig.chunks) {
for (auto &c : sig.__chunks) {
if (c.wire == NULL && (c.data.bits.at(0) == RTLIL::State::S1) && !hicell_celltype.empty()) {
if (!singleton_mode || last_hi.width == 0) {
last_hi = RTLIL::SigChunk(module->addWire(NEW_ID));

112
passes/techmap/simplemap.cc
View file

@ -42,8 +42,8 @@ static void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::Cell *gate = new RTLIL::Cell;
gate->name = NEW_ID;
gate->type = "$_INV_";
gate->connections["\\A"] = sig_a.chunks.at(i);
gate->connections["\\Y"] = sig_y.chunks.at(i);
gate->connections["\\A"] = sig_a.__chunks.at(i);
gate->connections["\\Y"] = sig_y.__chunks.at(i);
module->add(gate);
}
}
@ -96,8 +96,8 @@ static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::Cell *gate = new RTLIL::Cell;
gate->name = NEW_ID;
gate->type = "$_INV_";
gate->connections["\\A"] = sig_t.chunks.at(i);
gate->connections["\\Y"] = sig_y.chunks.at(i);
gate->connections["\\A"] = sig_t.__chunks.at(i);
gate->connections["\\Y"] = sig_y.__chunks.at(i);
module->add(gate);
}
@ -115,9 +115,9 @@ static void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::Cell *gate = new RTLIL::Cell;
gate->name = NEW_ID;
gate->type = gate_type;
gate->connections["\\A"] = sig_a.chunks.at(i);
gate->connections["\\B"] = sig_b.chunks.at(i);
gate->connections["\\Y"] = sig_y.chunks.at(i);
gate->connections["\\A"] = sig_a.__chunks.at(i);
gate->connections["\\B"] = sig_b.__chunks.at(i);
gate->connections["\\Y"] = sig_y.__chunks.at(i);
module->add(gate);
}
}
@ -129,20 +129,20 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::SigSpec sig_y = cell->connections.at("\\Y");
if (sig_y.width == 0)
if (sig_y.__width == 0)
return;
if (sig_a.width == 0) {
if (cell->type == "$reduce_and") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.width)));
if (cell->type == "$reduce_or") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.width)));
if (cell->type == "$reduce_xor") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.width)));
if (cell->type == "$reduce_xnor") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.width)));
if (cell->type == "$reduce_bool") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.width)));
if (sig_a.__width == 0) {
if (cell->type == "$reduce_and") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.__width)));
if (cell->type == "$reduce_or") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.__width)));
if (cell->type == "$reduce_xor") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.__width)));
if (cell->type == "$reduce_xnor") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(1, sig_y.__width)));
if (cell->type == "$reduce_bool") module->connections.push_back(RTLIL::SigSig(sig_y, RTLIL::SigSpec(0, sig_y.__width)));
return;
}
if (sig_y.width > 1) {
module->connections.push_back(RTLIL::SigSig(sig_y.extract(1, sig_y.width-1), RTLIL::SigSpec(0, sig_y.width-1)));
if (sig_y.__width > 1) {
module->connections.push_back(RTLIL::SigSig(sig_y.extract(1, sig_y.__width-1), RTLIL::SigSpec(0, sig_y.__width-1)));
sig_y = sig_y.extract(0, 1);
}
@ -156,24 +156,24 @@ static void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::SigSpec *last_output = NULL;
while (sig_a.width > 1)
while (sig_a.__width > 1)
{
RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig_a.width / 2);
RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig_a.__width / 2);
sig_t.expand();
for (int i = 0; i < sig_a.width; i += 2)
for (int i = 0; i < sig_a.__width; i += 2)
{
if (i+1 == sig_a.width) {
sig_t.append(sig_a.chunks.at(i));
if (i+1 == sig_a.__width) {
sig_t.append(sig_a.__chunks.at(i));
continue;
}
RTLIL::Cell *gate = new RTLIL::Cell;
gate->name = NEW_ID;
gate->type = gate_type;
gate->connections["\\A"] = sig_a.chunks.at(i);
gate->connections["\\B"] = sig_a.chunks.at(i+1);
gate->connections["\\Y"] = sig_t.chunks.at(i/2);
gate->connections["\\A"] = sig_a.__chunks.at(i);
gate->connections["\\B"] = sig_a.__chunks.at(i+1);
gate->connections["\\Y"] = sig_t.__chunks.at(i/2);
last_output = &gate->connections["\\Y"];
module->add(gate);
}
@ -204,31 +204,31 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig)
{
sig.expand();
while (sig.width > 1)
while (sig.__width > 1)
{
RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig.width / 2);
RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig.__width / 2);
sig_t.expand();
for (int i = 0; i < sig.width; i += 2)
for (int i = 0; i < sig.__width; i += 2)
{
if (i+1 == sig.width) {
sig_t.append(sig.chunks.at(i));
if (i+1 == sig.__width) {
sig_t.append(sig.__chunks.at(i));
continue;
}
RTLIL::Cell *gate = new RTLIL::Cell;
gate->name = NEW_ID;
gate->type = "$_OR_";
gate->connections["\\A"] = sig.chunks.at(i);
gate->connections["\\B"] = sig.chunks.at(i+1);
gate->connections["\\Y"] = sig_t.chunks.at(i/2);
gate->connections["\\A"] = sig.__chunks.at(i);
gate->connections["\\B"] = sig.__chunks.at(i+1);
gate->connections["\\Y"] = sig_t.__chunks.at(i/2);
module->add(gate);
}
sig = sig_t;
}
if (sig.width == 0)
if (sig.__width == 0)
sig = RTLIL::SigSpec(0, 1);
}
@ -239,11 +239,11 @@ static void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::SigSpec sig_y = cell->connections.at("\\Y");
if (sig_y.width == 0)
if (sig_y.__width == 0)
return;
if (sig_y.width > 1) {
module->connections.push_back(RTLIL::SigSig(sig_y.extract(1, sig_y.width-1), RTLIL::SigSpec(0, sig_y.width-1)));
if (sig_y.__width > 1) {
module->connections.push_back(RTLIL::SigSig(sig_y.extract(1, sig_y.__width-1), RTLIL::SigSpec(0, sig_y.__width-1)));
sig_y = sig_y.extract(0, 1);
}
@ -265,11 +265,11 @@ static void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::SigSpec sig_y = cell->connections.at("\\Y");
if (sig_y.width == 0)
if (sig_y.__width == 0)
return;
if (sig_y.width > 1) {
module->connections.push_back(RTLIL::SigSig(sig_y.extract(1, sig_y.width-1), RTLIL::SigSpec(0, sig_y.width-1)));
if (sig_y.__width > 1) {
module->connections.push_back(RTLIL::SigSig(sig_y.extract(1, sig_y.__width-1), RTLIL::SigSpec(0, sig_y.__width-1)));
sig_y = sig_y.extract(0, 1);
}
@ -304,10 +304,10 @@ static void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::Cell *gate = new RTLIL::Cell;
gate->name = NEW_ID;
gate->type = "$_MUX_";
gate->connections["\\A"] = sig_a.chunks.at(i);
gate->connections["\\B"] = sig_b.chunks.at(i);
gate->connections["\\A"] = sig_a.__chunks.at(i);
gate->connections["\\B"] = sig_b.__chunks.at(i);
gate->connections["\\S"] = cell->connections.at("\\S");
gate->connections["\\Y"] = sig_y.chunks.at(i);
gate->connections["\\Y"] = sig_y.__chunks.at(i);
module->add(gate);
}
}
@ -317,7 +317,7 @@ static void simplemap_slice(RTLIL::Module *module, RTLIL::Cell *cell)
int offset = cell->parameters.at("\\OFFSET").as_int();
RTLIL::SigSpec sig_a = cell->connections.at("\\A");
RTLIL::SigSpec sig_y = cell->connections.at("\\Y");
module->connections.push_back(RTLIL::SigSig(sig_y, sig_a.extract(offset, sig_y.width)));
module->connections.push_back(RTLIL::SigSig(sig_y, sig_a.extract(offset, sig_y.__width)));
}
static void simplemap_concat(RTLIL::Module *module, RTLIL::Cell *cell)
@ -349,9 +349,9 @@ static void simplemap_sr(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::Cell *gate = new RTLIL::Cell;
gate->name = NEW_ID;
gate->type = gate_type;
gate->connections["\\S"] = sig_s.chunks.at(i);
gate->connections["\\R"] = sig_r.chunks.at(i);
gate->connections["\\Q"] = sig_q.chunks.at(i);
gate->connections["\\S"] = sig_s.__chunks.at(i);
gate->connections["\\R"] = sig_r.__chunks.at(i);
gate->connections["\\Q"] = sig_q.__chunks.at(i);
module->add(gate);
}
}
@ -376,8 +376,8 @@ static void simplemap_dff(RTLIL::Module *module, RTLIL::Cell *cell)
gate->name = NEW_ID;
gate->type = gate_type;
gate->connections["\\C"] = sig_clk;
gate->connections["\\D"] = sig_d.chunks.at(i);
gate->connections["\\Q"] = sig_q.chunks.at(i);
gate->connections["\\D"] = sig_d.__chunks.at(i);
gate->connections["\\Q"] = sig_q.__chunks.at(i);
module->add(gate);
}
}
@ -410,10 +410,10 @@ static void simplemap_dffsr(RTLIL::Module *module, RTLIL::Cell *cell)
gate->name = NEW_ID;
gate->type = gate_type;
gate->connections["\\C"] = sig_clk;
gate->connections["\\S"] = sig_s.chunks.at(i);
gate->connections["\\R"] = sig_r.chunks.at(i);
gate->connections["\\D"] = sig_d.chunks.at(i);
gate->connections["\\Q"] = sig_q.chunks.at(i);
gate->connections["\\S"] = sig_s.__chunks.at(i);
gate->connections["\\R"] = sig_r.__chunks.at(i);
gate->connections["\\D"] = sig_d.__chunks.at(i);
gate->connections["\\Q"] = sig_q.__chunks.at(i);
module->add(gate);
}
}
@ -446,8 +446,8 @@ static void simplemap_adff(RTLIL::Module *module, RTLIL::Cell *cell)
gate->type = rst_val.at(i) == RTLIL::State::S1 ? gate_type_1 : gate_type_0;
gate->connections["\\C"] = sig_clk;
gate->connections["\\R"] = sig_rst;
gate->connections["\\D"] = sig_d.chunks.at(i);
gate->connections["\\Q"] = sig_q.chunks.at(i);
gate->connections["\\D"] = sig_d.__chunks.at(i);
gate->connections["\\Q"] = sig_q.__chunks.at(i);
module->add(gate);
}
}
@ -472,8 +472,8 @@ static void simplemap_dlatch(RTLIL::Module *module, RTLIL::Cell *cell)
gate->name = NEW_ID;
gate->type = gate_type;
gate->connections["\\E"] = sig_en;
gate->connections["\\D"] = sig_d.chunks.at(i);
gate->connections["\\Q"] = sig_q.chunks.at(i);
gate->connections["\\D"] = sig_d.__chunks.at(i);
gate->connections["\\Q"] = sig_q.__chunks.at(i);
module->add(gate);
}
}

18
passes/techmap/techmap.cc
View file

@ -41,13 +41,13 @@ static void apply_prefix(std::string prefix, std::string &id)
static void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module *module)
{
for (size_t i = 0; i < sig.chunks.size(); i++) {
if (sig.chunks[i].wire == NULL)
for (size_t i = 0; i < sig.__chunks.size(); i++) {
if (sig.__chunks[i].wire == NULL)
continue;
std::string wire_name = sig.chunks[i].wire->name;
std::string wire_name = sig.__chunks[i].wire->name;
apply_prefix(prefix, wire_name);
assert(module->wires.count(wire_name) > 0);
sig.chunks[i].wire = module->wires[wire_name];
sig.__chunks[i].wire = module->wires[wire_name];
}
}
@ -163,11 +163,11 @@ struct TechmapWorker
c.second = it.second;
apply_prefix(cell->name, c.first, module);
}
if (c.second.width > c.first.width)
c.second.remove(c.first.width, c.second.width - c.first.width);
if (c.second.width < c.first.width)
c.second.append(RTLIL::SigSpec(RTLIL::State::S0, c.first.width - c.second.width));
assert(c.first.width == c.second.width);
if (c.second.__width > c.first.__width)
c.second.remove(c.first.__width, c.second.__width - c.first.__width);
if (c.second.__width < c.first.__width)
c.second.append(RTLIL::SigSpec(RTLIL::State::S0, c.first.__width - c.second.__width));
assert(c.first.__width == c.second.__width);
if (flatten_mode) {
// more conservative approach:
// connect internal and external wires