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SigSpec refactoring: renamed chunks and width to __chunks and __width

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This commit is contained in:
Clifford Wolf 2014-07-22 19:56:17 +02:00
parent 3b5f4ff39c
commit a233762a81
62 changed files with 954 additions and 951 deletions
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4
passes/hierarchy/hierarchy.cc
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@ -61,7 +61,7 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
for (auto &conn : i2.second->connections) {
if (conn.first[0] != '$')
portnames.insert(conn.first);
portwidths[conn.first] = std::max(portwidths[conn.first], conn.second.width);
portwidths[conn.first] = std::max(portwidths[conn.first], conn.second.__width);
}
for (auto &para : i2.second->parameters)
parameters.insert(para.first);
@ -220,7 +220,7 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla
RTLIL::Module *mod = design->modules[cell->type];
for (auto &conn : cell->connections) {
int conn_size = conn.second.width;
int conn_size = conn.second.__width;
std::string portname = conn.first;
if (portname.substr(0, 1) == "$") {
int port_id = atoi(portname.substr(1).c_str());

4
passes/hierarchy/submod.cc
View file

@ -67,7 +67,7 @@ struct SubmodWorker
void flag_signal(RTLIL::SigSpec &sig, bool create, bool set_int_driven, bool set_int_used, bool set_ext_driven, bool set_ext_used)
{
for (auto &c : sig.chunks)
for (auto &c : sig.__chunks)
if (c.wire != NULL)
flag_wire(c.wire, create, set_int_driven, set_int_used, set_ext_driven, set_ext_used);
}
@ -164,7 +164,7 @@ struct SubmodWorker
for (RTLIL::Cell *cell : submod.cells) {
RTLIL::Cell *new_cell = new RTLIL::Cell(*cell);
for (auto &conn : new_cell->connections)
for (auto &c : conn.second.chunks)
for (auto &c : conn.second.__chunks)
if (c.wire != NULL) {
assert(wire_flags.count(c.wire) > 0);
c.wire = wire_flags[c.wire].new_wire;