mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-17 18:06:41 +00:00
Code Activity

SigSpec refactoring: renamed chunks and width to __chunks and __width

Browse source
This commit is contained in:
Clifford Wolf 2014-07-22 19:56:17 +02:00
parent 3b5f4ff39c
commit a233762a81
62 changed files with 954 additions and 951 deletions
Download patch file Download diff file Expand all files Collapse all files

18
passes/fsm/fsm_expand.cc
View file

@ -43,7 +43,7 @@ struct FsmExpand
bool is_cell_merge_candidate(RTLIL::Cell *cell)
{
if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux")
if (cell->connections.at("\\A").width < 2)
if (cell->connections.at("\\A").__width < 2)
return true;
RTLIL::SigSpec new_signals;
@ -62,7 +62,7 @@ struct FsmExpand
new_signals.remove(assign_map(fsm_cell->connections["\\CTRL_IN"]));
new_signals.remove(assign_map(fsm_cell->connections["\\CTRL_OUT"]));
if (new_signals.width > 3)
if (new_signals.__width > 3)
return false;
if (cell->connections.count("\\Y") > 0) {
@ -73,7 +73,7 @@ struct FsmExpand
new_signals.remove(assign_map(fsm_cell->connections["\\CTRL_OUT"]));
}
if (new_signals.width > 2)
if (new_signals.__width > 2)
return false;
return true;
@ -145,8 +145,8 @@ struct FsmExpand
std::vector<RTLIL::Const> truth_tab;
for (int i = 0; i < (1 << input_sig.width); i++) {
RTLIL::Const in_val(i, input_sig.width);
for (int i = 0; i < (1 << input_sig.__width); i++) {
RTLIL::Const in_val(i, input_sig.__width);
RTLIL::SigSpec A, B, S;
if (cell->connections.count("\\A") > 0)
A = assign_map(cell->connections["\\A"]);
@ -166,17 +166,17 @@ struct FsmExpand
FsmData fsm_data;
fsm_data.copy_from_cell(fsm_cell);
fsm_data.num_inputs += input_sig.width;
fsm_data.num_inputs += input_sig.__width;
fsm_cell->connections["\\CTRL_IN"].append(input_sig);
fsm_data.num_outputs += output_sig.width;
fsm_data.num_outputs += output_sig.__width;
fsm_cell->connections["\\CTRL_OUT"].append(output_sig);
std::vector<FsmData::transition_t> new_transition_table;
for (auto &tr : fsm_data.transition_table) {
for (int i = 0; i < (1 << input_sig.width); i++) {
for (int i = 0; i < (1 << input_sig.__width); i++) {
FsmData::transition_t new_tr = tr;
RTLIL::Const in_val(i, input_sig.width);
RTLIL::Const in_val(i, input_sig.__width);
RTLIL::Const out_val = truth_tab[i];
RTLIL::SigSpec ctrl_in = new_tr.ctrl_in;
RTLIL::SigSpec ctrl_out = new_tr.ctrl_out;