mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-29 07:27:58 +00:00
Code Activity

SigSpec refactoring: renamed chunks and width to __chunks and __width

Browse source
This commit is contained in:
Clifford Wolf 2014-07-22 19:56:17 +02:00
parent 3b5f4ff39c
commit a233762a81
62 changed files with 954 additions and 951 deletions
Download patch file Download diff file Expand all files Collapse all files

4
passes/fsm/fsm_detect.cc
View file

@ -56,8 +56,8 @@ static bool check_state_mux_tree(RTLIL::SigSpec old_sig, RTLIL::SigSpec sig, Sig
RTLIL::SigSpec sig_b = assign_map(cellport.first->connections["\\B"]);
if (!check_state_mux_tree(old_sig, sig_a, recursion_monitor))
return false;
for (int i = 0; i < sig_b.width; i += sig_a.width)
if (!check_state_mux_tree(old_sig, sig_b.extract(i, sig_a.width), recursion_monitor))
for (int i = 0; i < sig_b.__width; i += sig_a.__width)
if (!check_state_mux_tree(old_sig, sig_b.extract(i, sig_a.__width), recursion_monitor))
return false;
muxtree_cells.insert(cellport.first);
}

18
passes/fsm/fsm_expand.cc
View file

@ -43,7 +43,7 @@ struct FsmExpand
bool is_cell_merge_candidate(RTLIL::Cell *cell)
{
if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux")
if (cell->connections.at("\\A").width < 2)
if (cell->connections.at("\\A").__width < 2)
return true;
RTLIL::SigSpec new_signals;
@ -62,7 +62,7 @@ struct FsmExpand
new_signals.remove(assign_map(fsm_cell->connections["\\CTRL_IN"]));
new_signals.remove(assign_map(fsm_cell->connections["\\CTRL_OUT"]));
if (new_signals.width > 3)
if (new_signals.__width > 3)
return false;
if (cell->connections.count("\\Y") > 0) {
@ -73,7 +73,7 @@ struct FsmExpand
new_signals.remove(assign_map(fsm_cell->connections["\\CTRL_OUT"]));
}
if (new_signals.width > 2)
if (new_signals.__width > 2)
return false;
return true;
@ -145,8 +145,8 @@ struct FsmExpand
std::vector<RTLIL::Const> truth_tab;
for (int i = 0; i < (1 << input_sig.width); i++) {
RTLIL::Const in_val(i, input_sig.width);
for (int i = 0; i < (1 << input_sig.__width); i++) {
RTLIL::Const in_val(i, input_sig.__width);
RTLIL::SigSpec A, B, S;
if (cell->connections.count("\\A") > 0)
A = assign_map(cell->connections["\\A"]);
@ -166,17 +166,17 @@ struct FsmExpand
FsmData fsm_data;
fsm_data.copy_from_cell(fsm_cell);
fsm_data.num_inputs += input_sig.width;
fsm_data.num_inputs += input_sig.__width;
fsm_cell->connections["\\CTRL_IN"].append(input_sig);
fsm_data.num_outputs += output_sig.width;
fsm_data.num_outputs += output_sig.__width;
fsm_cell->connections["\\CTRL_OUT"].append(output_sig);
std::vector<FsmData::transition_t> new_transition_table;
for (auto &tr : fsm_data.transition_table) {
for (int i = 0; i < (1 << input_sig.width); i++) {
for (int i = 0; i < (1 << input_sig.__width); i++) {
FsmData::transition_t new_tr = tr;
RTLIL::Const in_val(i, input_sig.width);
RTLIL::Const in_val(i, input_sig.__width);
RTLIL::Const out_val = truth_tab[i];
RTLIL::SigSpec ctrl_in = new_tr.ctrl_in;
RTLIL::SigSpec ctrl_out = new_tr.ctrl_out;

38
passes/fsm/fsm_extract.cc
View file

@ -36,7 +36,7 @@ static SigSet<sig2driver_entry_t> sig2driver, sig2trigger;
static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL::SigSpec &ctrl, std::map<RTLIL::Const, int> &states, RTLIL::Const *reset_state = NULL)
{
sig.extend(dff_out.width, false);
sig.extend(dff_out.__width, false);
if (sig == dff_out)
return true;
@ -44,10 +44,10 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL
assign_map.apply(sig);
if (sig.is_fully_const()) {
sig.optimize();
assert(sig.chunks.size() == 1);
if (states.count(sig.chunks[0].data) == 0) {
assert(sig.__chunks.size() == 1);
if (states.count(sig.__chunks[0].data) == 0) {
log(" found state code: %s\n", log_signal(sig));
states[sig.chunks[0].data] = -1;
states[sig.__chunks[0].data] = -1;
}
return true;
}
@ -73,14 +73,14 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL
break;
log(" found reset state: %s (guessed from mux tree)\n", log_signal(*reset_state));
} while (0);
if (ctrl.extract(sig_s).width == 0) {
if (ctrl.extract(sig_s).__width == 0) {
log(" found ctrl input: %s\n", log_signal(sig_s));
ctrl.append(sig_s);
}
if (!find_states(sig_a, dff_out, ctrl, states))
return false;
for (int i = 0; i < sig_b.width/sig_a.width; i++) {
if (!find_states(sig_b.extract(i*sig_a.width, sig_a.width), dff_out, ctrl, states))
for (int i = 0; i < sig_b.__width/sig_a.__width; i++) {
if (!find_states(sig_b.extract(i*sig_a.__width, sig_a.__width), dff_out, ctrl, states))
return false;
}
}
@ -90,11 +90,11 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL
static RTLIL::Const sig2const(ConstEval &ce, RTLIL::SigSpec sig, RTLIL::State noconst_state, RTLIL::SigSpec dont_care = RTLIL::SigSpec())
{
if (dont_care.width > 0) {
if (dont_care.__width > 0) {
sig.expand();
for (auto &chunk : sig.chunks) {
for (auto &chunk : sig.__chunks) {
assert(chunk.width == 1);
if (dont_care.extract(chunk).width > 0)
if (dont_care.extract(chunk).__width > 0)
chunk.wire = NULL, chunk.data = RTLIL::Const(noconst_state);
}
sig.optimize();
@ -104,17 +104,17 @@ static RTLIL::Const sig2const(ConstEval &ce, RTLIL::SigSpec sig, RTLIL::State no
ce.values_map.apply(sig);
sig.expand();
for (auto &chunk : sig.chunks) {
for (auto &chunk : sig.__chunks) {
assert(chunk.width == 1);
if (chunk.wire != NULL)
chunk.wire = NULL, chunk.data = RTLIL::Const(noconst_state);
}
sig.optimize();
if (sig.width == 0)
if (sig.__width == 0)
return RTLIL::Const();
assert(sig.chunks.size() == 1 && sig.chunks[0].wire == NULL);
return sig.chunks[0].data;
assert(sig.__chunks.size() == 1 && sig.__chunks[0].wire == NULL);
return sig.__chunks[0].data;
}
static void find_transitions(ConstEval &ce, ConstEval &ce_nostop, FsmData &fsm_data, std::map<RTLIL::Const, int> &states, int state_in, RTLIL::SigSpec ctrl_in, RTLIL::SigSpec ctrl_out, RTLIL::SigSpec dff_in, RTLIL::SigSpec dont_care)
@ -144,7 +144,7 @@ static void find_transitions(ConstEval &ce, ConstEval &ce_nostop, FsmData &fsm_d
return;
}
log_assert(undef.width > 0);
log_assert(undef.__width > 0);
log_assert(ce.stop_signals.check_all(undef));
undef = undef.extract(0, 1);
@ -258,8 +258,8 @@ static void extract_fsm(RTLIL::Wire *wire)
// Initialize fsm data struct
FsmData fsm_data;
fsm_data.num_inputs = ctrl_in.width;
fsm_data.num_outputs = ctrl_out.width;
fsm_data.num_inputs = ctrl_in.__width;
fsm_data.num_outputs = ctrl_out.__width;
fsm_data.state_bits = wire->width;
fsm_data.reset_state = -1;
for (auto &it : states) {
@ -314,7 +314,7 @@ static void extract_fsm(RTLIL::Wire *wire)
RTLIL::SigSpec unconn_sig = port_sig.extract(ctrl_out);
RTLIL::Wire *unconn_wire = new RTLIL::Wire;
unconn_wire->name = stringf("$fsm_unconnect$%s$%d", log_signal(unconn_sig), RTLIL::autoidx++);
unconn_wire->width = unconn_sig.width;
unconn_wire->width = unconn_sig.__width;
module->wires[unconn_wire->name] = unconn_wire;
port_sig.replace(unconn_sig, RTLIL::SigSpec(unconn_wire), &cell->connections[cellport.second]);
}
@ -367,7 +367,7 @@ struct FsmExtractPass : public Pass {
sig2driver.insert(sig, sig2driver_entry_t(cell_it.first, conn_it.first));
}
if (ct.cell_input(cell_it.second->type, conn_it.first) && cell_it.second->connections.count("\\Y") > 0 &&
cell_it.second->connections["\\Y"].width == 1 && (conn_it.first == "\\A" || conn_it.first == "\\B")) {
cell_it.second->connections["\\Y"].__width == 1 && (conn_it.first == "\\A" || conn_it.first == "\\B")) {
RTLIL::SigSpec sig = conn_it.second;
assign_map.apply(sig);
sig2trigger.insert(sig, sig2driver_entry_t(cell_it.first, conn_it.first));

30
passes/fsm/fsm_map.cc
View file

@ -50,12 +50,12 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
or_sig.append(RTLIL::SigSpec(state_onehot, 1, in_state));
or_sig.optimize();
if (or_sig.width == 0)
if (or_sig.__width == 0)
continue;
RTLIL::SigSpec and_sig;
if (eq_sig_a.width > 0)
if (eq_sig_a.__width > 0)
{
RTLIL::Wire *eq_wire = new RTLIL::Wire;
eq_wire->name = NEW_ID;
@ -69,17 +69,17 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
eq_cell->connections["\\Y"] = RTLIL::SigSpec(eq_wire);
eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false);
eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(eq_sig_a.width);
eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(eq_sig_b.width);
eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(eq_sig_a.__width);
eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(eq_sig_b.__width);
eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
module->add(eq_cell);
and_sig.append(RTLIL::SigSpec(eq_wire));
}
if (or_sig.width < num_states-int(fullstate_cache.size()))
if (or_sig.__width < num_states-int(fullstate_cache.size()))
{
if (or_sig.width == 1)
if (or_sig.__width == 1)
{
and_sig.append(or_sig);
}
@ -95,7 +95,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
or_cell->connections["\\A"] = or_sig;
or_cell->connections["\\Y"] = RTLIL::SigSpec(or_wire);
or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(or_sig.width);
or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(or_sig.__width);
or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
module->add(or_cell);
@ -103,7 +103,7 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
}
}
switch (and_sig.width)
switch (and_sig.__width)
{
case 2:
{
@ -138,17 +138,17 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
}
}
if (cases_vector.width > 1) {
if (cases_vector.__width > 1) {
RTLIL::Cell *or_cell = new RTLIL::Cell;
or_cell->name = NEW_ID;
or_cell->type = "$reduce_or";
or_cell->connections["\\A"] = cases_vector;
or_cell->connections["\\Y"] = output;
or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cases_vector.width);
or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cases_vector.__width);
or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
module->add(or_cell);
} else if (cases_vector.width == 1) {
} else if (cases_vector.__width == 1) {
module->connections.push_back(RTLIL::SigSig(output, cases_vector));
} else {
module->connections.push_back(RTLIL::SigSig(output, RTLIL::SigSpec(0, 1)));
@ -237,8 +237,8 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
eq_cell->connections["\\Y"] = RTLIL::SigSpec(state_onehot, 1, i);
eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false);
eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_a.width);
eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(sig_b.width);
eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_a.__width);
eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(sig_b.__width);
eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
module->add(eq_cell);
}
@ -308,8 +308,8 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
mux_cell->connections["\\B"] = sig_b;
mux_cell->connections["\\S"] = sig_s;
mux_cell->connections["\\Y"] = RTLIL::SigSpec(next_state_wire);
mux_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_a.width);
mux_cell->parameters["\\S_WIDTH"] = RTLIL::Const(sig_s.width);
mux_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_a.__width);
mux_cell->parameters["\\S_WIDTH"] = RTLIL::Const(sig_s.__width);
module->add(mux_cell);
}

18
passes/fsm/fsm_opt.cc
View file

@ -33,11 +33,11 @@ struct FsmOpt
bool signal_is_unused(RTLIL::SigSpec sig)
{
assert(sig.width == 1);
assert(sig.__width == 1);
sig.optimize();
RTLIL::Wire *wire = sig.chunks[0].wire;
int bit = sig.chunks[0].offset;
RTLIL::Wire *wire = sig.__chunks[0].wire;
int bit = sig.__chunks[0].offset;
if (!wire || wire->attributes.count("\\unused_bits") == 0)
return false;
@ -55,11 +55,11 @@ struct FsmOpt
void opt_const_and_unused_inputs()
{
RTLIL::SigSpec ctrl_in = cell->connections["\\CTRL_IN"];
std::vector<bool> ctrl_in_used(ctrl_in.width);
std::vector<bool> ctrl_in_used(ctrl_in.__width);
std::vector<FsmData::transition_t> new_transition_table;
for (auto &tr : fsm_data.transition_table) {
for (int i = 0; i < ctrl_in.width; i++) {
for (int i = 0; i < ctrl_in.__width; i++) {
RTLIL::SigSpec ctrl_bit = ctrl_in.extract(i, 1);
if (ctrl_bit.is_fully_const()) {
if (tr.ctrl_in.bits[i] <= RTLIL::State::S1 && RTLIL::SigSpec(tr.ctrl_in.bits[i]) != ctrl_bit)
@ -112,8 +112,8 @@ struct FsmOpt
{
RTLIL::SigSpec &ctrl_in = cell->connections["\\CTRL_IN"];
for (int i = 0; i < ctrl_in.width; i++)
for (int j = i+1; j < ctrl_in.width; j++)
for (int i = 0; i < ctrl_in.__width; i++)
for (int j = i+1; j < ctrl_in.__width; j++)
if (ctrl_in.extract(i, 1) == ctrl_in.extract(j, 1))
{
log(" Optimize handling of signal %s that is connected to inputs %d and %d.\n", log_signal(ctrl_in.extract(i, 1)), i, j);
@ -150,8 +150,8 @@ struct FsmOpt
RTLIL::SigSpec &ctrl_in = cell->connections["\\CTRL_IN"];
RTLIL::SigSpec &ctrl_out = cell->connections["\\CTRL_OUT"];
for (int j = 0; j < ctrl_out.width; j++)
for (int i = 0; i < ctrl_in.width; i++)
for (int j = 0; j < ctrl_out.__width; j++)
for (int i = 0; i < ctrl_in.__width; i++)
if (ctrl_in.extract(i, 1) == ctrl_out.extract(j, 1))
{
log(" Optimize handling of signal %s that is connected to input %d and output %d.\n", log_signal(ctrl_in.extract(i, 1)), i, j);

8
passes/fsm/fsmdata.h
View file

@ -143,15 +143,15 @@ struct FsmData
log(" Input signals:\n");
RTLIL::SigSpec sig_in = cell->connections["\\CTRL_IN"];
sig_in.expand();
for (size_t i = 0; i < sig_in.chunks.size(); i++)
log(" %3zd: %s\n", i, log_signal(sig_in.chunks[i]));
for (size_t i = 0; i < sig_in.__chunks.size(); i++)
log(" %3zd: %s\n", i, log_signal(sig_in.__chunks[i]));
log("\n");
log(" Output signals:\n");
RTLIL::SigSpec sig_out = cell->connections["\\CTRL_OUT"];
sig_out.expand();
for (size_t i = 0; i < sig_out.chunks.size(); i++)
log(" %3zd: %s\n", i, log_signal(sig_out.chunks[i]));
for (size_t i = 0; i < sig_out.__chunks.size(); i++)
log(" %3zd: %s\n", i, log_signal(sig_out.__chunks[i]));
log("\n");
log(" State encoding:\n");