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SigSpec refactoring: renamed chunks and width to __chunks and __width

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This commit is contained in:
Clifford Wolf 2014-07-22 19:56:17 +02:00
parent 3b5f4ff39c
commit a233762a81
62 changed files with 954 additions and 951 deletions
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8
passes/cmds/connwrappers.cc
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@ -90,7 +90,7 @@ struct ConnwrappersWorker
continue;
int inner_width = cell->parameters.at(decl.widthparam).as_int();
int outer_width = conn.second.width;
int outer_width = conn.second.__width;
bool is_signed = decl.signparam.empty() ? decl.is_signed : cell->parameters.at(decl.signparam).as_bool();
if (inner_width >= outer_width)
@ -124,20 +124,20 @@ struct ConnwrappersWorker
int extend_width = 0;
RTLIL::SigBit extend_bit = is_signed ? sigbits[i] : RTLIL::SigBit(RTLIL::State::S0);
while (extend_width < extend_sig.width && i + extend_width + 1 < sigbits.size() &&
while (extend_width < extend_sig.__width && i + extend_width + 1 < sigbits.size() &&
sigbits[i + extend_width + 1] == extend_bit) extend_width++;
if (extend_width == 0)
continue;
if (old_sig.width == 0)
if (old_sig.__width == 0)
old_sig = conn.second;
conn.second.replace(i+1, extend_sig.extract(0, extend_width));
i += extend_width;
}
if (old_sig.width)
if (old_sig.__width)
log("Connected extended bits of %s.%s:%s: %s -> %s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name),
RTLIL::id2cstr(conn.first), log_signal(old_sig), log_signal(conn.second));
}