mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-22 22:03:40 +00:00
Code Activity

SigSpec refactoring: renamed chunks and width to __chunks and __width

Browse source
This commit is contained in:
Clifford Wolf 2014-07-22 19:56:17 +02:00
parent 3b5f4ff39c
commit a233762a81
62 changed files with 954 additions and 951 deletions
Download patch file Download diff file Expand all files Collapse all files

2
passes/cmds/connect.cc
View file

@ -27,7 +27,7 @@ static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap &
{
CellTypes ct(design);
RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.width);
RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.__width);
for (auto &it : module->cells)
for (auto &port : it.second->connections)