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SigSpec refactoring: renamed chunks and width to __chunks and __width

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This commit is contained in:
Clifford Wolf 2014-07-22 19:56:17 +02:00
parent 3b5f4ff39c
commit a233762a81
62 changed files with 954 additions and 951 deletions
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10
passes/abc/blifparse.cc
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@ -177,10 +177,10 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name)
}
input_sig.append(wire);
}
output_sig = input_sig.extract(input_sig.width-1, 1);
input_sig = input_sig.extract(0, input_sig.width-1);
output_sig = input_sig.extract(input_sig.__width-1, 1);
input_sig = input_sig.extract(0, input_sig.__width-1);
if (input_sig.width == 0) {
if (input_sig.__width == 0) {
RTLIL::State state = RTLIL::State::Sa;
while (1) {
if (!read_next_line(buffer, buffer_size, line_count, f))
@ -218,8 +218,8 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name)
RTLIL::Cell *cell = new RTLIL::Cell;
cell->name = NEW_ID;
cell->type = "$lut";
cell->parameters["\\WIDTH"] = RTLIL::Const(input_sig.width);
cell->parameters["\\LUT"] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.width);
cell->parameters["\\WIDTH"] = RTLIL::Const(input_sig.__width);
cell->parameters["\\LUT"] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.__width);
cell->connections["\\I"] = input_sig;
cell->connections["\\O"] = output_sig;
lutptr = &cell->parameters.at("\\LUT");