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SigSpec refactoring: renamed chunks and width to __chunks and __width

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This commit is contained in:
Clifford Wolf 2014-07-22 19:56:17 +02:00
parent 3b5f4ff39c
commit a233762a81
62 changed files with 954 additions and 951 deletions
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12
kernel/bitpattern.h
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@ -31,16 +31,16 @@ struct BitPatternPool
BitPatternPool(RTLIL::SigSpec sig)
{
width = sig.width;
width = sig.__width;
if (width > 0) {
std::vector<RTLIL::State> pattern(width);
sig.optimize();
for (int i = 0; i < width; i++) {
RTLIL::SigSpec s = sig.extract(i, 1);
s.optimize();
assert(s.chunks.size() == 1);
if (s.chunks[0].wire == NULL && s.chunks[0].data.bits[0] <= RTLIL::State::S1)
pattern[i] = s.chunks[0].data.bits[0];
assert(s.__chunks.size() == 1);
if (s.__chunks[0].wire == NULL && s.__chunks[0].data.bits[0] <= RTLIL::State::S1)
pattern[i] = s.__chunks[0].data.bits[0];
else
pattern[i] = RTLIL::State::Sa;
}
@ -63,8 +63,8 @@ struct BitPatternPool
{
sig.optimize();
assert(sig.is_fully_const());
assert(sig.chunks.size() == 1);
bits_t bits = sig.chunks[0].data.bits;
assert(sig.__chunks.size() == 1);
bits_t bits = sig.__chunks[0].data.bits;
for (auto &b : bits)
if (b > RTLIL::State::S1)
b = RTLIL::State::Sa;