mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-07 06:33:24 +00:00
Code Activity

SigSpec refactoring: renamed chunks and width to __chunks and __width

Browse source
This commit is contained in:
Clifford Wolf 2014-07-22 19:56:17 +02:00
parent 3b5f4ff39c
commit a233762a81
62 changed files with 954 additions and 951 deletions
Download patch file Download diff file Expand all files Collapse all files

8
backends/ilang/ilang_backend.cc
View file

@ -102,11 +102,11 @@ void ILANG_BACKEND::dump_sigchunk(FILE *f, const RTLIL::SigChunk &chunk, bool au
void ILANG_BACKEND::dump_sigspec(FILE *f, const RTLIL::SigSpec &sig, bool autoint)
{
if (sig.chunks.size() == 1) {
dump_sigchunk(f, sig.chunks[0], autoint);
if (sig.__chunks.size() == 1) {
dump_sigchunk(f, sig.__chunks[0], autoint);
} else {
fprintf(f, "{ ");
for (auto it = sig.chunks.rbegin(); it != sig.chunks.rend(); it++) {
for (auto it = sig.__chunks.rbegin(); it != sig.__chunks.rend(); it++) {
dump_sigchunk(f, *it, false);
fprintf(f, " ");
}
@ -314,7 +314,7 @@ void ILANG_BACKEND::dump_module(FILE *f, std::string indent, const RTLIL::Module
if (only_selected) {
RTLIL::SigSpec sigs = it->first;
sigs.append(it->second);
for (auto &c : sigs.chunks) {
for (auto &c : sigs.__chunks) {
if (c.wire == NULL || !design->selected(module, c.wire))
continue;
show_conn = true;