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SigSpec refactoring: renamed chunks and width to __chunks and __width

This commit is contained in:
Clifford Wolf 2014-07-22 19:56:17 +02:00
parent 3b5f4ff39c
commit a233762a81
62 changed files with 954 additions and 951 deletions

View file

@ -119,8 +119,8 @@ static void autotest(FILE *f, RTLIL::Design *design)
if ((*it4)->type == RTLIL::ST0 || (*it4)->type == RTLIL::ST1)
continue;
RTLIL::SigSpec &signal = (*it4)->signal;
for (size_t i = 0; i < signal.chunks.size(); i++) {
if (signal.chunks[i].wire == wire)
for (size_t i = 0; i < signal.__chunks.size(); i++) {
if (signal.__chunks[i].wire == wire)
is_clksignal = true;
}
}