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SigSpec refactoring: renamed chunks and width to __chunks and __width
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62 changed files with 954 additions and 951 deletions
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@ -119,8 +119,8 @@ static void autotest(FILE *f, RTLIL::Design *design)
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if ((*it4)->type == RTLIL::ST0 || (*it4)->type == RTLIL::ST1)
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continue;
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RTLIL::SigSpec &signal = (*it4)->signal;
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for (size_t i = 0; i < signal.chunks.size(); i++) {
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if (signal.chunks[i].wire == wire)
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for (size_t i = 0; i < signal.__chunks.size(); i++) {
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if (signal.__chunks[i].wire == wire)
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is_clksignal = true;
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}
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}
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