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Fix ecp5 tests

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- remove *_synth.v files and generation in scripts;
- change synth_ice40 to synth_ecp5;
This commit is contained in:
SergeyDegtyar 2019-09-04 12:15:52 +03:00
parent 55fbc1a355
commit a203c8569c
11 changed files with 26 additions and 2421 deletions
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6
tests/ecp5/logic.ys
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@ -1,7 +1,7 @@
read_verilog logic.v
hierarchy -top top
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 9 t:SB_LUT4
select -assert-none t:SB_LUT4 %% t:* %D
select -assert-count 9 t:LUT4
select -assert-none t:LUT4 %% t:* %D