mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-30 09:17:13 +00:00
Code Activity

Fix ecp5 tests

Browse source 
- remove *_synth.v files and generation in scripts;
- change synth_ice40 to synth_ecp5;
This commit is contained in:
SergeyDegtyar 2019-09-04 12:15:52 +03:00
parent 55fbc1a355
commit a203c8569c
11 changed files with 26 additions and 2421 deletions
Download patch file Download diff file Expand all files Collapse all files

9
tests/ecp5/counter.ys
View file

@ -2,10 +2,9 @@ read_verilog counter.v
hierarchy -top top
proc
flatten
equiv_opt -map +/ice40/cells_sim.v synth_ice40 # equivalency check
equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 6 t:SB_CARRY
select -assert-count 8 t:SB_DFFR
select -assert-count 8 t:SB_LUT4
select -assert-none t:SB_CARRY t:SB_DFFR t:SB_LUT4 %% t:* %D
select -assert-count 4 t:CCU2C
select -assert-count 8 t:TRELLIS_FF
select -assert-none t:CCU2C t:TRELLIS_FF %% t:* %D