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https://github.com/YosysHQ/yosys
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Add option for using assoc list helpers in tests
This commit is contained in:
Gus Smith
parent
8a9d724873
commit
a1d68fe3bc
3 changed files with 91 additions and 187 deletions
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@ -43,21 +43,37 @@ def write_vcd(filename: Path, signals: SignalStepMap, timescale='1 ns', date='to
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if change_time == time:
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f.write(f"{value} {signal_name}\n")
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def simulate_rosette(rkt_file_path: Path, vcd_path: Path, num_steps: int, rnd: Random):
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def simulate_rosette(
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rkt_file_path: Path,
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vcd_path: Path,
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num_steps: int,
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rnd: Random,
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use_assoc_list_helpers: bool = False,
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):
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"""
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Args:
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- use_assoc_list_helpers: If True, will use the association list helpers
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in the Racket file. The file should have been generated with the
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-assoc-list-helpers flag in the yosys command.
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"""
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signals: dict[str, list[str]] = {}
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inputs: SignalWidthMap = {}
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outputs: SignalWidthMap = {}
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current_struct_name: str = ""
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with open(rkt_file_path, 'r') as rkt_file:
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with open(rkt_file_path, "r") as rkt_file:
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for line in rkt_file:
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m = re.search(r'gold_(Inputs|Outputs|State)', line)
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m = re.search(r"gold_(Inputs|Outputs|State)", line)
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if m:
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current_struct_name = m.group(1)
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if current_struct_name == "State": break
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elif not current_struct_name: continue # skip lines before structs
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m = re.search(r'; (.+?)\b \(bitvector (\d+)\)', line)
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if not m: continue # skip non matching lines (probably closing the struct)
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if current_struct_name == "State":
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break
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elif not current_struct_name:
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continue # skip lines before structs
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m = re.search(r"; (.+?)\b \(bitvector (\d+)\)", line)
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if not m:
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continue # skip non matching lines (probably closing the struct)
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signal = m.group(1)
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width = int(m.group(2))
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if current_struct_name == "Inputs":
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@ -69,43 +85,86 @@ def simulate_rosette(rkt_file_path: Path, vcd_path: Path, num_steps: int, rnd: R
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step_list: list[int] = []
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for step in range(num_steps):
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value = rnd.getrandbits(width)
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binary_string = format(value, '0{}b'.format(width))
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binary_string = format(value, "0{}b".format(width))
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step_list.append(binary_string)
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signals[signal] = step_list
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test_rkt_file_path = rkt_file_path.with_suffix('.tst.rkt')
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with open(test_rkt_file_path, 'w') as test_rkt_file:
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test_rkt_file.writelines([
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'#lang rosette\n',
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test_rkt_file_path = rkt_file_path.with_suffix(".tst.rkt")
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with open(test_rkt_file_path, "w") as test_rkt_file:
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test_rkt_file.writelines(
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[
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"#lang rosette\n",
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f'(require "{rkt_file_path.name}")\n',
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])
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]
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)
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for step in range(num_steps):
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this_step = f"step_{step}"
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value_list: list[str] = []
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if use_assoc_list_helpers:
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# Generate inputs as a list of cons pairs making up the
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# association list.
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for signal, width in inputs.items():
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value = signals[signal][step]
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value_list.append(f'(cons "{signal}" (bv #b{value} {width}))')
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else:
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# Otherwise, we generate the inputs as a list of bitvectors.
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for signal, width in inputs.items():
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value = signals[signal][step]
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value_list.append(f"(bv #b{value} {width})")
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gold_Inputs = f"(gold_Inputs {' '.join(value_list)})"
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gold_Inputs = (
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f"(gold_inputs_helper (list {' '.join(value_list)}))"
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if use_assoc_list_helpers
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else f"(gold_Inputs {' '.join(value_list)})"
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)
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gold_State = f"(cdr step_{step-1})" if step else "gold_initial"
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test_rkt_file.write(f"(define {this_step} (gold {gold_Inputs} {gold_State})) (car {this_step})\n")
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get_value_expr = (
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f"(gold_outputs_helper (car {this_step}))"
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if use_assoc_list_helpers
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else f"(car {this_step})"
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)
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test_rkt_file.write(
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f"(define {this_step} (gold {gold_Inputs} {gold_State})) {get_value_expr}\n"
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)
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cmd = ["racket", test_rkt_file_path]
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status = subprocess.run(cmd, capture_output=True)
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assert status.returncode == 0, f"{cmd[0]} failed"
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try:
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status = subprocess.run(cmd, capture_output=True, check=True)
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except subprocess.CalledProcessError as e:
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raise RuntimeError(
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f"Racket simulation failed with command: {cmd}\n"
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f"Error: {e.stderr.decode()}"
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) from e
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for signal in outputs.keys():
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signals[signal] = []
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for line in status.stdout.decode().splitlines():
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m = re.match(r'\(gold_Outputs( \(bv \S+ \d+\))+\)', line)
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m = (
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re.match(r"\(list( \(cons \"\S+\" \(bv \S+ \d+\)\))+\)", line)
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if use_assoc_list_helpers
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else re.match(r"\(gold_Outputs( \(bv \S+ \d+\))+\)", line)
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)
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assert m, f"Incomplete output definition {line!r}"
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for output, (value, width) in zip(outputs.keys(), re.findall(r'\(bv (\S+) (\d+)\)', line)):
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outputs_values_and_widths = (
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{
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output: re.findall(
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r"\(cons \"" + output + r"\" \(bv (\S+) (\d+)\)\)", line
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)[0]
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for output in outputs.keys()
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}.items()
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if use_assoc_list_helpers
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else zip(outputs.keys(), re.findall(r"\(bv (\S+) (\d+)\)", line))
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)
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for output, (value, width) in outputs_values_and_widths:
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assert isinstance(value, str), f"Bad value {value!r}"
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assert value.startswith(('#b', '#x')), f"Non-binary value {value!r}"
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assert int(width) == outputs[output], f"Width mismatch for output {output!r} (got {width}, expected {outputs[output]})"
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int_value = int(value[2:], 16 if value.startswith('#x') else 2)
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binary_string = format(int_value, '0{}b'.format(width))
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assert value.startswith(("#b", "#x")), f"Non-binary value {value!r}"
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assert (
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int(width) == outputs[output]
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), f"Width mismatch for output {output!r} (got {width}, expected {outputs[output]})"
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int_value = int(value[2:], 16 if value.startswith("#x") else 2)
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binary_string = format(int_value, "0{}b".format(width))
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signals[output].append(binary_string)
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vcd_signals: SignalStepMap = {}
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@ -1,157 +0,0 @@
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; Utilities for simulating Rosette programs.
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;
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; Tests can be run with `raco test <this file>`.
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#lang racket/base
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(provide simulate-rosette)
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(require (only-in rosette bv)
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racket/list)
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; Inputs:
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; - function: The function for the module to simulate. This should be a Rosette function generated by
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; Yosys's `write_fuctional_rosette` backend.
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; - initial-state: The initial state of the module, as generated by Yosys's `write_fuctional_rosette`
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; backend.
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; - inputs: A list of association lists. The function will be called with each association list as
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; inputs, and the state will be threaded through each call.
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;
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; Outputs:
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; - A list of outputs, one for each cycle. The outputs are a list of the output objects generated by
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; `function`.
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(define (simulate-rosette #:function function #:initial-state initial-state #:inputs inputs)
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(define outputs-and-states
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(drop (reverse (foldl (lambda (input acc)
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(let* ([outputs (function input (cdr (car acc)))]) (cons outputs acc)))
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(list (cons 'unused initial-state))
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inputs))
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1))
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(define outputs (map car outputs-and-states))
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outputs)
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; Inputs:
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; - inputs: association list mapping string name to bitwidth.
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; - num-inputs: number of inputs to generate.
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; TODO(@gussmith23): If `num-inputs` is more than the number of possible values, just enumerate.
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(define (generate-inputs #:inputs inputs #:num-inputs num-inputs)
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(define (generate-random-input inputs)
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(map (lambda (pair) (cons (car pair) (bv (random (expt 2 (cdr pair))) (cdr pair)))) inputs))
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(for/list ([_ (range num-inputs)])
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(generate-random-input inputs)))
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; Generates a clock signal for the given inputs.
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;
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; Given a string of inputs, one per clock cycle, this function generates a clock signal alongside the
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; inputs. It does so by alternating the clock signal between 0 and 1 for each cycle, starting with 0.
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; For example, if the inputs are (list inputs1 inputs2 inputs3), the output will be (list (cons (cons
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; "clk" (bv 0 1)) inputs1) (cons (cons "clk" (bv 1 1)) inputs1) (cons (cons "clk" (bv 0 1)) inputs2)
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; (cons (cons "clk" (bv 1 1)) inputs2) ... ).
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;
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; Inputs:
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; - clock-name: The name of the clock signal.
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; - inputs: A list of inputs in association list form, as output by `generate-inputs`.
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;
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; Outputs:
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; - A list of association lists, each containing a new clock signal. Will be twice the length of the
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; inputs list.
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(define (generate-clock #:clock-name clock-name #:inputs inputs)
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(apply append
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(for/list ([this-cycle-inputs inputs])
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(list (cons (cons clock-name (bv 0 1)) this-cycle-inputs)
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(cons (cons clock-name (bv 1 1)) this-cycle-inputs)))))
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; This is what gets executed when the script is run.
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(module main racket/base
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(require racket/cmdline)
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; - input-helper, output-helper: association-list-based helpers for input and output struct, generated
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; by Yosys's `write_fuctional_rosette` backend with `-assoc-list-helpers` enabled.
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)
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(module+ test
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(require rackunit
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(only-in rosette bv bvadd))
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(test-case "generate-inputs"
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(check-equal? (length (generate-inputs #:inputs (list (cons "input1" 4)) #:num-inputs 10)) 10)
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; Check that this call generates a list of one-length lists, each containing a single association
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; list with the key "input1" and a random value.
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(check-true (foldl (lambda (input acc)
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(and acc (equal? (length input) 1) (equal? (car (first input)) "input1")))
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#t
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(generate-inputs #:inputs (list (cons "input1" 4)) #:num-inputs 10))))
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(test-case "generate-clock"
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(define inputs
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(list (list (cons "input1" (bv 4 4)) (cons "input2" (bv 3 3)) (cons "input3" (bv 2 2)))
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(list (cons "input1" (bv 3 4)) (cons "input2" (bv 4 3)) (cons "input3" (bv 1 2)))
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(list (cons "input1" (bv 2 4)) (cons "input2" (bv 5 3)) (cons "input3" (bv 0 2)))))
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(check-equal? (length (generate-clock #:clock-name "clk" #:inputs inputs)) 6)
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(check-equal?
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(generate-clock #:clock-name "clk" #:inputs inputs)
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(list (cons (cons "clk" (bv 0 1))
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(list (cons "input1" (bv 4 4)) (cons "input2" (bv 3 3)) (cons "input3" (bv 2 2))))
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(cons (cons "clk" (bv 1 1))
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(list (cons "input1" (bv 4 4)) (cons "input2" (bv 3 3)) (cons "input3" (bv 2 2))))
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(cons (cons "clk" (bv 0 1))
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(list (cons "input1" (bv 3 4)) (cons "input2" (bv 4 3)) (cons "input3" (bv 1 2))))
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(cons (cons "clk" (bv 1 1))
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(list (cons "input1" (bv 3 4)) (cons "input2" (bv 4 3)) (cons "input3" (bv 1 2))))
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(cons (cons "clk" (bv 0 1))
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(list (cons "input1" (bv 2 4)) (cons "input2" (bv 5 3)) (cons "input3" (bv 0 2))))
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(cons (cons "clk" (bv 1 1))
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(list (cons "input1" (bv 2 4)) (cons "input2" (bv 5 3)) (cons "input3" (bv 0 2)))))))
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(test-case "simulate-rosette"
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; This function will take association lists as inputs, so the helper function is simply identity.
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; This is not generally true of Yosys-generated code. Similarly, this function uses an association
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; list for state, which is not what Yosys generates, but it's easier for testing.
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;
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; A one-stage adder. Inputs are registered in one clock cycle, and the output is the sum of the
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; two registered inputs.
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(define (module-function inputs state)
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(let* ([a (cdr (assoc "a" inputs))]
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[b (cdr (assoc "b" inputs))]
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[clk (cdr (assoc "clk" inputs))]
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[old-clk (cdr (assoc "clk" state))]
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[prev-a (cdr (assoc "prev-a" state))]
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[prev-b (cdr (assoc "prev-b" state))]
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[a-reg (cdr (assoc "a-reg" state))]
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[b-reg (cdr (assoc "b-reg" state))]
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[clk-ticked (and (equal? clk (bv 1 1)) (equal? old-clk (bv 0 1)))]
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[new-a-reg (if clk-ticked prev-a a-reg)]
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[new-b-reg (if clk-ticked prev-b b-reg)]
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[out (list (cons "o" (bvadd new-a-reg new-b-reg)))]
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[new-state (list (cons "prev-a" a)
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(cons "a-reg" new-a-reg)
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(cons "prev-b" b)
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(cons "b-reg" new-b-reg)
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(cons "clk" clk))])
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(cons out new-state)))
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(define outputs
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(simulate-rosette #:function module-function
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#:initial-state (list (cons "a-reg" (bv 0 4))
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(cons "b-reg" (bv 0 4))
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(cons "prev-a" (bv 0 4))
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(cons "prev-b" (bv 0 4))
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(cons "clk" (bv 0 1)))
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#:inputs
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(list (list (cons "clk" (bv 0 1)) (cons "a" (bv 4 4)) (cons "b" (bv 4 4)))
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(list (cons "clk" (bv 1 1)) (cons "a" (bv 3 4)) (cons "b" (bv 0 4)))
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(list (cons "clk" (bv 0 1)) (cons "a" (bv 10 4)) (cons "b" (bv 9 4)))
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(list (cons "clk" (bv 1 1)) (cons "a" (bv 2 4)) (cons "b" (bv -1 4)))
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(list (cons "clk" (bv 0 1)) (cons "a" (bv 4 4)) (cons "b" (bv -15 4)))
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(list (cons "clk" (bv 1 1)) (cons "a" (bv 0 4)) (cons "b" (bv 0 4))))))
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(check-equal? outputs
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(list (list (cons "o" (bv 0 4)))
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(list (cons "o" (bv 8 4)))
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(list (cons "o" (bv 8 4)))
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(list (cons "o" (bv 3 4)))
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(list (cons "o" (bv 3 4)))
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(list (cons "o" (bv -11 4)))))))
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@ -74,7 +74,8 @@ def test_smt(cell, parameters, tmp_path, num_steps, rnd):
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yosys_sim(rtlil_file, vcd_functional_file, vcd_yosys_sim_file, getattr(cell, 'sim_preprocessing', ''))
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@pytest.mark.rkt
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def test_rkt(cell, parameters, tmp_path, num_steps, rnd):
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@pytest.mark.parametrize("use_assoc_list_helpers", [True, False])
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def test_rkt(cell, parameters, tmp_path, num_steps, rnd, use_assoc_list_helpers):
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import rkt_vcd
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rtlil_file = tmp_path / 'rtlil.il'
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@ -83,8 +84,9 @@ def test_rkt(cell, parameters, tmp_path, num_steps, rnd):
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vcd_yosys_sim_file = tmp_path / 'yosys.vcd'
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cell.write_rtlil_file(rtlil_file, parameters)
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yosys(f"read_rtlil {quote(rtlil_file)} ; clk2fflogic ; write_functional_rosette -provides {quote(rkt_file)}")
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rkt_vcd.simulate_rosette(rkt_file, vcd_functional_file, num_steps, rnd(cell.name + "-rkt"))
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use_assoc_helpers_flag = '-assoc-list-helpers' if use_assoc_list_helpers else ''
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yosys(f"read_rtlil {quote(rtlil_file)} ; clk2fflogic ; write_functional_rosette -provides {use_assoc_helpers_flag} {quote(rkt_file)}")
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rkt_vcd.simulate_rosette(rkt_file, vcd_functional_file, num_steps, rnd(cell.name + "-rkt"), use_assoc_list_helpers=use_assoc_list_helpers)
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yosys_sim(rtlil_file, vcd_functional_file, vcd_yosys_sim_file, getattr(cell, 'sim_preprocessing', ''))
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def test_print_graph(tmp_path):
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