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https://github.com/YosysHQ/yosys
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Add option for using assoc list helpers in tests
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parent
8a9d724873
commit
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3 changed files with 91 additions and 187 deletions
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@ -43,21 +43,37 @@ def write_vcd(filename: Path, signals: SignalStepMap, timescale='1 ns', date='to
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if change_time == time:
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f.write(f"{value} {signal_name}\n")
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def simulate_rosette(rkt_file_path: Path, vcd_path: Path, num_steps: int, rnd: Random):
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def simulate_rosette(
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rkt_file_path: Path,
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vcd_path: Path,
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num_steps: int,
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rnd: Random,
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use_assoc_list_helpers: bool = False,
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):
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"""
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Args:
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- use_assoc_list_helpers: If True, will use the association list helpers
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in the Racket file. The file should have been generated with the
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-assoc-list-helpers flag in the yosys command.
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"""
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signals: dict[str, list[str]] = {}
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inputs: SignalWidthMap = {}
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outputs: SignalWidthMap = {}
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current_struct_name: str = ""
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with open(rkt_file_path, 'r') as rkt_file:
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with open(rkt_file_path, "r") as rkt_file:
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for line in rkt_file:
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m = re.search(r'gold_(Inputs|Outputs|State)', line)
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m = re.search(r"gold_(Inputs|Outputs|State)", line)
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if m:
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current_struct_name = m.group(1)
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if current_struct_name == "State": break
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elif not current_struct_name: continue # skip lines before structs
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m = re.search(r'; (.+?)\b \(bitvector (\d+)\)', line)
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if not m: continue # skip non matching lines (probably closing the struct)
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if current_struct_name == "State":
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break
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elif not current_struct_name:
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continue # skip lines before structs
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m = re.search(r"; (.+?)\b \(bitvector (\d+)\)", line)
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if not m:
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continue # skip non matching lines (probably closing the struct)
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signal = m.group(1)
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width = int(m.group(2))
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if current_struct_name == "Inputs":
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@ -69,43 +85,86 @@ def simulate_rosette(rkt_file_path: Path, vcd_path: Path, num_steps: int, rnd: R
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step_list: list[int] = []
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for step in range(num_steps):
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value = rnd.getrandbits(width)
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binary_string = format(value, '0{}b'.format(width))
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binary_string = format(value, "0{}b".format(width))
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step_list.append(binary_string)
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signals[signal] = step_list
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test_rkt_file_path = rkt_file_path.with_suffix('.tst.rkt')
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with open(test_rkt_file_path, 'w') as test_rkt_file:
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test_rkt_file.writelines([
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'#lang rosette\n',
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f'(require "{rkt_file_path.name}")\n',
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])
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test_rkt_file_path = rkt_file_path.with_suffix(".tst.rkt")
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with open(test_rkt_file_path, "w") as test_rkt_file:
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test_rkt_file.writelines(
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[
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"#lang rosette\n",
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f'(require "{rkt_file_path.name}")\n',
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]
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)
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for step in range(num_steps):
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this_step = f"step_{step}"
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value_list: list[str] = []
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for signal, width in inputs.items():
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value = signals[signal][step]
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value_list.append(f"(bv #b{value} {width})")
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gold_Inputs = f"(gold_Inputs {' '.join(value_list)})"
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if use_assoc_list_helpers:
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# Generate inputs as a list of cons pairs making up the
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# association list.
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for signal, width in inputs.items():
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value = signals[signal][step]
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value_list.append(f'(cons "{signal}" (bv #b{value} {width}))')
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else:
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# Otherwise, we generate the inputs as a list of bitvectors.
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for signal, width in inputs.items():
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value = signals[signal][step]
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value_list.append(f"(bv #b{value} {width})")
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gold_Inputs = (
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f"(gold_inputs_helper (list {' '.join(value_list)}))"
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if use_assoc_list_helpers
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else f"(gold_Inputs {' '.join(value_list)})"
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)
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gold_State = f"(cdr step_{step-1})" if step else "gold_initial"
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test_rkt_file.write(f"(define {this_step} (gold {gold_Inputs} {gold_State})) (car {this_step})\n")
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get_value_expr = (
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f"(gold_outputs_helper (car {this_step}))"
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if use_assoc_list_helpers
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else f"(car {this_step})"
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)
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test_rkt_file.write(
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f"(define {this_step} (gold {gold_Inputs} {gold_State})) {get_value_expr}\n"
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)
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cmd = ["racket", test_rkt_file_path]
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status = subprocess.run(cmd, capture_output=True)
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assert status.returncode == 0, f"{cmd[0]} failed"
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try:
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status = subprocess.run(cmd, capture_output=True, check=True)
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except subprocess.CalledProcessError as e:
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raise RuntimeError(
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f"Racket simulation failed with command: {cmd}\n"
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f"Error: {e.stderr.decode()}"
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) from e
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for signal in outputs.keys():
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signals[signal] = []
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for line in status.stdout.decode().splitlines():
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m = re.match(r'\(gold_Outputs( \(bv \S+ \d+\))+\)', line)
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m = (
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re.match(r"\(list( \(cons \"\S+\" \(bv \S+ \d+\)\))+\)", line)
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if use_assoc_list_helpers
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else re.match(r"\(gold_Outputs( \(bv \S+ \d+\))+\)", line)
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)
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assert m, f"Incomplete output definition {line!r}"
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for output, (value, width) in zip(outputs.keys(), re.findall(r'\(bv (\S+) (\d+)\)', line)):
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outputs_values_and_widths = (
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{
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output: re.findall(
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r"\(cons \"" + output + r"\" \(bv (\S+) (\d+)\)\)", line
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)[0]
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for output in outputs.keys()
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}.items()
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if use_assoc_list_helpers
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else zip(outputs.keys(), re.findall(r"\(bv (\S+) (\d+)\)", line))
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)
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for output, (value, width) in outputs_values_and_widths:
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assert isinstance(value, str), f"Bad value {value!r}"
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assert value.startswith(('#b', '#x')), f"Non-binary value {value!r}"
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assert int(width) == outputs[output], f"Width mismatch for output {output!r} (got {width}, expected {outputs[output]})"
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int_value = int(value[2:], 16 if value.startswith('#x') else 2)
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binary_string = format(int_value, '0{}b'.format(width))
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assert value.startswith(("#b", "#x")), f"Non-binary value {value!r}"
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assert (
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int(width) == outputs[output]
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), f"Width mismatch for output {output!r} (got {width}, expected {outputs[output]})"
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int_value = int(value[2:], 16 if value.startswith("#x") else 2)
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binary_string = format(int_value, "0{}b".format(width))
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signals[output].append(binary_string)
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vcd_signals: SignalStepMap = {}
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