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Avoid parameter values with size 0 ($mem cells)

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This commit is contained in:
Clifford Wolf 2015-04-05 18:04:19 +02:00
parent 95944eb69e
commit a1c62b79d5
3 changed files with 16 additions and 11 deletions
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10
kernel/rtlil.cc
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@ -918,11 +918,11 @@ namespace {
param("\\SIZE"); param("\\SIZE");
param("\\OFFSET"); param("\\OFFSET");
param("\\INIT"); param("\\INIT");
param_bits("\\RD_CLK_ENABLE", param("\\RD_PORTS")); param_bits("\\RD_CLK_ENABLE", std::max(1, param("\\RD_PORTS")));
param_bits("\\RD_CLK_POLARITY", param("\\RD_PORTS")); param_bits("\\RD_CLK_POLARITY", std::max(1, param("\\RD_PORTS")));
param_bits("\\RD_TRANSPARENT", param("\\RD_PORTS")); param_bits("\\RD_TRANSPARENT", std::max(1, param("\\RD_PORTS")));
param_bits("\\WR_CLK_ENABLE", param("\\WR_PORTS")); param_bits("\\WR_CLK_ENABLE", std::max(1, param("\\WR_PORTS")));
param_bits("\\WR_CLK_POLARITY", param("\\WR_PORTS")); param_bits("\\WR_CLK_POLARITY", std::max(1, param("\\WR_PORTS")));
port("\\RD_CLK", param("\\RD_PORTS")); port("\\RD_CLK", param("\\RD_PORTS"));
port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS")); port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS"));
port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH")); port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH"));

10
passes/memory/memory_collect.cc
View file

@ -178,8 +178,8 @@ void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
log_assert(sig_wr_en.size() == wr_ports * memory->width); log_assert(sig_wr_en.size() == wr_ports * memory->width);
mem->parameters["\\WR_PORTS"] = RTLIL::Const(wr_ports); mem->parameters["\\WR_PORTS"] = RTLIL::Const(wr_ports);
mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.as_const() : RTLIL::Const(0, 0); mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.as_const() : RTLIL::Const(0, 1);
mem->parameters["\\WR_CLK_POLARITY"] = wr_ports ? sig_wr_clk_polarity.as_const() : RTLIL::Const(0, 0); mem->parameters["\\WR_CLK_POLARITY"] = wr_ports ? sig_wr_clk_polarity.as_const() : RTLIL::Const(0, 1);
mem->setPort("\\WR_CLK", sig_wr_clk); mem->setPort("\\WR_CLK", sig_wr_clk);
mem->setPort("\\WR_ADDR", sig_wr_addr); mem->setPort("\\WR_ADDR", sig_wr_addr);
@ -193,9 +193,9 @@ void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
log_assert(sig_rd_data.size() == rd_ports * memory->width); log_assert(sig_rd_data.size() == rd_ports * memory->width);
mem->parameters["\\RD_PORTS"] = RTLIL::Const(rd_ports); mem->parameters["\\RD_PORTS"] = RTLIL::Const(rd_ports);
mem->parameters["\\RD_CLK_ENABLE"] = rd_ports ? sig_rd_clk_enable.as_const() : RTLIL::Const(0, 0); mem->parameters["\\RD_CLK_ENABLE"] = rd_ports ? sig_rd_clk_enable.as_const() : RTLIL::Const(0, 1);
mem->parameters["\\RD_CLK_POLARITY"] = rd_ports ? sig_rd_clk_polarity.as_const() : RTLIL::Const(0, 0); mem->parameters["\\RD_CLK_POLARITY"] = rd_ports ? sig_rd_clk_polarity.as_const() : RTLIL::Const(0, 1);
mem->parameters["\\RD_TRANSPARENT"] = rd_ports ? sig_rd_transparent.as_const() : RTLIL::Const(0, 0); mem->parameters["\\RD_TRANSPARENT"] = rd_ports ? sig_rd_transparent.as_const() : RTLIL::Const(0, 1);
mem->setPort("\\RD_CLK", sig_rd_clk); mem->setPort("\\RD_CLK", sig_rd_clk);
mem->setPort("\\RD_ADDR", sig_rd_addr); mem->setPort("\\RD_ADDR", sig_rd_addr);

7
passes/memory/memory_map.cc
View file

@ -81,6 +81,9 @@ struct MemoryMapWorker
std::set<int> static_ports; std::set<int> static_ports;
std::map<int, RTLIL::SigSpec> static_cells_map; std::map<int, RTLIL::SigSpec> static_cells_map;
int wr_ports = cell->parameters["\\WR_PORTS"].as_int();
int rd_ports = cell->parameters["\\RD_PORTS"].as_int();
int mem_size = cell->parameters["\\SIZE"].as_int(); int mem_size = cell->parameters["\\SIZE"].as_int();
int mem_width = cell->parameters["\\WIDTH"].as_int(); int mem_width = cell->parameters["\\WIDTH"].as_int();
int mem_offset = cell->parameters["\\OFFSET"].as_int(); int mem_offset = cell->parameters["\\OFFSET"].as_int();
@ -90,7 +93,7 @@ struct MemoryMapWorker
init_data.extend_u0(mem_size*mem_width, true); init_data.extend_u0(mem_size*mem_width, true);
// delete unused memory cell // delete unused memory cell
if (cell->parameters["\\RD_PORTS"].as_int() == 0 && cell->parameters["\\WR_PORTS"].as_int() == 0) { if (wr_ports == 0 && rd_ports == 0) {
module->remove(cell); module->remove(cell);
return; return;
} }
@ -99,6 +102,8 @@ struct MemoryMapWorker
RTLIL::SigSpec clocks = cell->getPort("\\WR_CLK"); RTLIL::SigSpec clocks = cell->getPort("\\WR_CLK");
RTLIL::Const clocks_pol = cell->parameters["\\WR_CLK_POLARITY"]; RTLIL::Const clocks_pol = cell->parameters["\\WR_CLK_POLARITY"];
RTLIL::Const clocks_en = cell->parameters["\\WR_CLK_ENABLE"]; RTLIL::Const clocks_en = cell->parameters["\\WR_CLK_ENABLE"];
clocks_pol.bits.resize(wr_ports);
clocks_en.bits.resize(wr_ports);
RTLIL::SigSpec refclock; RTLIL::SigSpec refclock;
RTLIL::State refclock_pol = RTLIL::State::Sx; RTLIL::State refclock_pol = RTLIL::State::Sx;
for (int i = 0; i < clocks.size(); i++) { for (int i = 0; i < clocks.size(); i++) {