mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-23 17:15:33 +00:00
Avoid parameter values with size 0 ($mem cells)
This commit is contained in:
parent
95944eb69e
commit
a1c62b79d5
3 changed files with 16 additions and 11 deletions
|
@ -918,11 +918,11 @@ namespace {
|
|||
param("\\SIZE");
|
||||
param("\\OFFSET");
|
||||
param("\\INIT");
|
||||
param_bits("\\RD_CLK_ENABLE", param("\\RD_PORTS"));
|
||||
param_bits("\\RD_CLK_POLARITY", param("\\RD_PORTS"));
|
||||
param_bits("\\RD_TRANSPARENT", param("\\RD_PORTS"));
|
||||
param_bits("\\WR_CLK_ENABLE", param("\\WR_PORTS"));
|
||||
param_bits("\\WR_CLK_POLARITY", param("\\WR_PORTS"));
|
||||
param_bits("\\RD_CLK_ENABLE", std::max(1, param("\\RD_PORTS")));
|
||||
param_bits("\\RD_CLK_POLARITY", std::max(1, param("\\RD_PORTS")));
|
||||
param_bits("\\RD_TRANSPARENT", std::max(1, param("\\RD_PORTS")));
|
||||
param_bits("\\WR_CLK_ENABLE", std::max(1, param("\\WR_PORTS")));
|
||||
param_bits("\\WR_CLK_POLARITY", std::max(1, param("\\WR_PORTS")));
|
||||
port("\\RD_CLK", param("\\RD_PORTS"));
|
||||
port("\\RD_ADDR", param("\\RD_PORTS") * param("\\ABITS"));
|
||||
port("\\RD_DATA", param("\\RD_PORTS") * param("\\WIDTH"));
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue