3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-24 05:08:56 +00:00

Strictly zero-extend unsigned A-inputs of shift operations

This commit is contained in:
Clifford Wolf 2014-03-06 11:53:37 +01:00
parent b1b8fe3a56
commit a1bfde8c5e
2 changed files with 3 additions and 3 deletions

View file

@ -305,14 +305,14 @@ static RTLIL::Const const_shift(const RTLIL::Const &arg1, const RTLIL::Const &ar
RTLIL::Const RTLIL::const_shl(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool, int result_len)
{
RTLIL::Const arg1_ext = arg1;
extend(arg1_ext, result_len, signed1);
extend_u0(arg1_ext, result_len, signed1);
return const_shift(arg1_ext, arg2, false, -1, result_len);
}
RTLIL::Const RTLIL::const_shr(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool, int result_len)
{
RTLIL::Const arg1_ext = arg1;
extend(arg1_ext, result_len, signed1);
extend_u0(arg1_ext, result_len, signed1);
return const_shift(arg1_ext, arg2, false, +1, result_len);
}