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split muxes synth per type

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This commit is contained in:
Miodrag Milanovic 2019-10-04 09:39:22 +02:00
parent 36af102801
commit a198bcdd4f
2 changed files with 39 additions and 39 deletions
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43
tests/xilinx/mux.ys
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@ -1,10 +1,45 @@
read_verilog mux.v
design -save read
proc
flatten
hierarchy -top mux2
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
cd mux2 # Constrain all select calls below inside the top module
select -assert-count 1 t:LUT3
select -assert-none t:LUT3 %% t:* %D
design -load read
proc
hierarchy -top mux4
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux4 # Constrain all select calls below inside the top module
select -assert-count 1 t:LUT6
select -assert-none t:LUT6 %% t:* %D
design -load read
proc
hierarchy -top mux8
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux8 # Constrain all select calls below inside the top module
select -assert-count 1 t:LUT3
select -assert-count 2 t:LUT6
select -assert-count 2 t:LUT3
select -assert-count 5 t:LUT6
select -assert-none t:LUT3 t:LUT6 %% t:* %D
design -load read
proc
hierarchy -top mux16
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mux16 # Constrain all select calls below inside the top module
select -assert-count 5 t:LUT6
select -assert-none t:LUT6 %% t:* %D