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Fix for abc_scc_break is bus

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This commit is contained in:
Eddie Hung 2019-06-24 22:16:56 -07:00
parent 5605002d8a
commit a19226c174
1 changed files with 23 additions and 21 deletions
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8
passes/techmap/abc9.cc
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@ -121,8 +121,8 @@ void handle_loops(RTLIL::Design *design)
if (it == cell->connections_.end()) if (it == cell->connections_.end())
log_error("abc_scc_break attribute value '%s' does not exist as port on module '%s'\n", jt->second.decode_string().c_str(), log_id(box_module)); log_error("abc_scc_break attribute value '%s' does not exist as port on module '%s'\n", jt->second.decode_string().c_str(), log_id(box_module));
log_assert(it != cell->connections_.end()); log_assert(it != cell->connections_.end());
auto &c = *it; RTLIL::SigSpec sig;
SigBit b = cell->getPort(RTLIL::escape_id(jt->second.decode_string())); for (auto b : it->second) {
Wire *w = b.wire; Wire *w = b.wire;
if (w->port_output) { if (w->port_output) {
log_assert(w->get_bool_attribute("\\abc_scc_break")); log_assert(w->get_bool_attribute("\\abc_scc_break"));
@ -145,7 +145,9 @@ void handle_loops(RTLIL::Design *design)
log_assert(b.offset < GetSize(w)); log_assert(b.offset < GetSize(w));
} }
} }
c.second = RTLIL::SigBit(w, b.offset); sig.append(RTLIL::SigBit(w, b.offset));
}
it->second = sig;
} }
} }
} }