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https://github.com/YosysHQ/yosys
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impl csa tree.
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nella
parent
de99d67bbd
commit
a180a0003f
2 changed files with 358 additions and 0 deletions
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@ -24,6 +24,7 @@ OBJS += passes/opt/opt_ffinv.o
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OBJS += passes/opt/pmux2shiftx.o
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OBJS += passes/opt/muxpack.o
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OBJS += passes/opt/opt_balance_tree.o
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OBJS += passes/opt/csa_tree.o
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OBJS += passes/opt/peepopt.o
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GENFILES += passes/opt/peepopt_pm.h
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357
passes/opt/csa_tree.cc
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357
passes/opt/csa_tree.cc
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@ -0,0 +1,357 @@
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct CsaTreeWorker
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{
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RTLIL::Module *module;
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SigMap sigmap;
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int min_operands;
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dict<RTLIL::SigBit, RTLIL::Cell*> sig_to_driver;
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dict<RTLIL::Cell*, int> cell_fanout;
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pool<RTLIL::Cell*> consumed;
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int stat_trees = 0;
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int stat_fa_cells = 0;
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int stat_removed_cells = 0;
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CsaTreeWorker(RTLIL::Module *module, int min_operands) :
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module(module), sigmap(module), min_operands(min_operands) {}
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void build_maps()
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{
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dict<RTLIL::SigBit, int> sig_consumers;
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for (auto cell : module->cells())
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{
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if (cell->type.in(ID($add), ID($sub)))
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{
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RTLIL::SigSpec y = sigmap(cell->getPort(ID::Y));
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for (auto bit : y)
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if (bit.wire != nullptr)
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sig_to_driver[bit] = cell;
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}
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for (auto &conn : cell->connections())
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{
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if (cell->input(conn.first))
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{
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for (auto bit : sigmap(conn.second))
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if (bit.wire != nullptr)
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sig_consumers[bit]++;
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}
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}
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}
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for (auto wire : module->wires())
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if (wire->port_output)
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for (auto bit : sigmap(wire))
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if (bit.wire != nullptr)
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sig_consumers[bit]++;
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for (auto cell : module->cells())
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{
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if (!cell->type.in(ID($add), ID($sub)))
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continue;
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int fo = 0;
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for (auto bit : sigmap(cell->getPort(ID::Y)))
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if (bit.wire != nullptr)
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fo = std::max(fo, sig_consumers.count(bit) ? sig_consumers.at(bit) : 0);
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cell_fanout[cell] = fo;
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}
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}
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struct Operand {
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RTLIL::SigSpec sig;
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bool is_signed;
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bool do_subtract;
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};
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bool can_absorb(RTLIL::Cell *cell)
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{
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if (cell == nullptr)
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return false;
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if (!cell->type.in(ID($add), ID($sub)))
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return false;
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if (consumed.count(cell))
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return false;
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if (cell_fanout.count(cell) ? cell_fanout.at(cell) != 1 : true)
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return false;
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return true;
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}
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RTLIL::Cell *get_driver(RTLIL::SigSpec sig)
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{
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sig = sigmap(sig);
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if (sig.empty())
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return nullptr;
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RTLIL::Cell *driver = nullptr;
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for (auto bit : sig)
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{
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if (bit.wire == nullptr)
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continue;
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auto it = sig_to_driver.find(bit);
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if (it == sig_to_driver.end())
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return nullptr;
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if (driver == nullptr)
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driver = it->second;
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else if (driver != it->second)
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return nullptr; // mixed
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}
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return driver;
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}
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void collect_operands(
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RTLIL::Cell *cell,
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bool negate,
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std::vector<Operand> &operands,
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std::vector<RTLIL::Cell*> &tree_cells
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) {
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tree_cells.push_back(cell);
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consumed.insert(cell);
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bool a_signed = cell->getParam(ID::A_SIGNED).as_bool();
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bool b_signed = cell->getParam(ID::B_SIGNED).as_bool();
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bool is_sub = (cell->type == ID($sub));
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RTLIL::SigSpec sig_a = cell->getPort(ID::A);
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RTLIL::SigSpec sig_b = cell->getPort(ID::B);
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RTLIL::Cell *driver_a = get_driver(sig_a);
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if (can_absorb(driver_a)) {
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collect_operands(driver_a, negate, operands, tree_cells);
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} else {
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operands.push_back({sig_a, a_signed, negate});
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}
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bool b_negate = negate ^ is_sub;
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RTLIL::Cell *driver_b = get_driver(sig_b);
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if (can_absorb(driver_b)) {
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collect_operands(driver_b, b_negate, operands, tree_cells);
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} else {
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operands.push_back({sig_b, b_signed, b_negate});
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}
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}
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void create_fa(
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RTLIL::SigSpec a,
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RTLIL::SigSpec b,
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RTLIL::SigSpec c,
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int width,
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RTLIL::SigSpec &sum_out,
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RTLIL::SigSpec &carry_out
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) {
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RTLIL::Wire *w_sum = module->addWire(NEW_ID, width);
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RTLIL::Wire *w_carry = module->addWire(NEW_ID, width);
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RTLIL::Cell *fa = module->addCell(NEW_ID, ID($fa));
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fa->setParam(ID::WIDTH, width);
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fa->setPort(ID::A, a);
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fa->setPort(ID::B, b);
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fa->setPort(ID::C, c);
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fa->setPort(ID::Y, w_sum);
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fa->setPort(ID::X, w_carry);
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sum_out = w_sum;
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carry_out = w_carry;
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stat_fa_cells++;
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}
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RTLIL::SigSpec extend_to(RTLIL::SigSpec sig, bool is_signed, int target_width)
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{
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if (GetSize(sig) >= target_width)
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return sig.extract(0, target_width);
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RTLIL::SigSpec result = sig;
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RTLIL::SigBit pad = is_signed ? sig[GetSize(sig) - 1] : RTLIL::S0;
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while (GetSize(result) < target_width)
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result.append(pad);
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return result;
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}
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RTLIL::SigSpec build_csa_tree(std::vector<Operand> &operands, int output_width)
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{
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int width = output_width;
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std::vector<RTLIL::SigSpec> summands;
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int sub_count = 0;
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for (auto &op : operands)
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{
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RTLIL::SigSpec sig = extend_to(op.sig, op.is_signed, width);
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if (op.do_subtract) {
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sig = module->Not(NEW_ID, sig);
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sub_count++;
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}
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summands.push_back(sig);
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}
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if (sub_count > 0) {
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RTLIL::Const correction(sub_count, width);
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summands.push_back(RTLIL::SigSpec(correction));
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}
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if (summands.empty())
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return RTLIL::SigSpec(0, width);
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if (summands.size() == 1)
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return summands[0];
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if (summands.size() == 2) {
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RTLIL::Wire *result = module->addWire(NEW_ID, width);
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module->addAdd(NEW_ID, summands[0], summands[1], result);
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return result;
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}
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while (summands.size() > 2)
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{
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std::vector<RTLIL::SigSpec> next;
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int i = 0;
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while (i + 2 < (int)summands.size())
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{
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RTLIL::SigSpec a = summands[i];
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RTLIL::SigSpec b = summands[i + 1];
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RTLIL::SigSpec c = summands[i + 2];
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RTLIL::SigSpec sum, carry;
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create_fa(a, b, c, width, sum, carry);
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RTLIL::SigSpec carry_shifted;
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carry_shifted.append(RTLIL::S0);
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carry_shifted.append(carry.extract(0, width - 1));
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next.push_back(sum);
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next.push_back(carry_shifted);
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i += 3;
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}
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while (i < (int)summands.size())
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next.push_back(summands[i++]);
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summands.swap(next);
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}
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RTLIL::Wire *result = module->addWire(NEW_ID, width);
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module->addAdd(NEW_ID, summands[0], summands[1], result);
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return result;
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}
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void run()
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{
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build_maps();
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std::vector<RTLIL::Cell*> roots;
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for (auto cell : module->selected_cells())
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if (cell->type.in(ID($add), ID($sub)))
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roots.push_back(cell);
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std::sort(roots.begin(), roots.end(),
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[](RTLIL::Cell *a, RTLIL::Cell *b) {
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return a->name < b->name;
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});
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std::sort(roots.begin(), roots.end(),
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[&](RTLIL::Cell *a, RTLIL::Cell *b) {
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return (cell_fanout.count(a) ? cell_fanout.at(a) : 0) >
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(cell_fanout.count(b) ? cell_fanout.at(b) : 0);
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});
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for (auto root : roots)
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{
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if (consumed.count(root))
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continue;
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std::vector<Operand> operands;
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std::vector<RTLIL::Cell*> tree_cells;
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collect_operands(root, false, operands, tree_cells);
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if ((int)operands.size() < min_operands) {
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for (auto c : tree_cells)
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consumed.erase(c);
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continue;
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}
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int output_width = root->getParam(ID::Y_WIDTH).as_int();
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log(" Found adder tree rooted at %s with %d operands (depth %d cells)\n",
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log_id(root), (int)operands.size(), (int)tree_cells.size());
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RTLIL::SigSpec new_output = build_csa_tree(operands, output_width);
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RTLIL::SigSpec old_output = root->getPort(ID::Y);
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module->connect(old_output, new_output);
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for (auto c : tree_cells) {
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module->remove(c);
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stat_removed_cells++;
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}
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stat_trees++;
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}
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}
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};
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struct CsaTreePass : public Pass
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{
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CsaTreePass() : Pass("csa_tree",
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"convert adder chains to carry-save adder trees") {}
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" csa_tree [options] [selection]\n");
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log("\n");
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log("This pass converts chains of $add/$sub cells into carry-save adder trees using\n");
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log("$fa (full adder / 3:2 compressor) cells to reduce the critical path depth of\n");
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log("multi-operand addition.\n");
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log("\n");
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log("For N operands of width W, the critical path is reduced from\n");
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log("O(N * log W) to O(log_1.5(N) + log W).\n");
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log("\n");
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log(" -min_operands N\n");
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log(" Minimum number of operands to trigger CSA tree construction.\n");
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log(" Default: 3. Values below 3 are clamped to 3.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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int min_operands = 3;
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log_header(design, "Executing CSA_TREE pass (carry-save adder tree optimization).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-min_operands" && argidx + 1 < args.size()) {
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min_operands = std::max(3, atoi(args[++argidx].c_str()));
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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{
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log("Processing module %s...\n", log_id(module));
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CsaTreeWorker worker(module, min_operands);
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worker.run();
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if (worker.stat_trees > 0)
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log(" Converted %d adder tree(s): created %d $fa cells, "
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"removed %d $add/$sub cells.\n",
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worker.stat_trees, worker.stat_fa_cells,
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worker.stat_removed_cells);
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}
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}
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} CsaTreePass;
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PRIVATE_NAMESPACE_END
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