mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 11:42:30 +00:00
Code Activity

Simplify test case script

Browse source
This commit is contained in:
Eddie Hung 2020-04-20 11:54:10 -07:00
parent 99a0958601
commit a1573058e9
1 changed files with 17 additions and 30 deletions
Download patch file Download diff file Expand all files Collapse all files

47
tests/various/dynamic_part_select.ys
View file

@ -1,13 +1,11 @@
### Original testcase ### ### Original testcase ###
read_verilog ./dynamic_part_select/original.v read_verilog ./dynamic_part_select/original.v
hierarchy -top original; proc; opt; proc
prep -flatten -top original
rename -top gold rename -top gold
design -stash gold design -stash gold
read_verilog ./dynamic_part_select/original_gate.v read_verilog ./dynamic_part_select/original_gate.v
hierarchy -top original_gate; proc; opt; proc
prep -flatten -top original_gate
rename -top gate rename -top gate
design -stash gate design -stash gate
@ -15,19 +13,17 @@ design -copy-from gold -as gold gold
design -copy-from gate -as gate gate design -copy-from gate -as gate gate
miter -equiv -make_assert -make_outcmp -flatten gold gate equiv miter -equiv -make_assert -make_outcmp -flatten gold gate equiv
hierarchy -top equiv
sat -prove-asserts -seq 10 -show-public -verify -set-init-zero -ignore_unknown_cells equiv sat -prove-asserts -seq 10 -show-public -verify -set-init-zero -ignore_unknown_cells equiv
### Multiple blocking assingments ### ### Multiple blocking assingments ###
design -reset
read_verilog ./dynamic_part_select/multiple_blocking.v read_verilog ./dynamic_part_select/multiple_blocking.v
hierarchy -top multiple_blocking; proc; opt; proc
prep -flatten -top multiple_blocking
rename -top gold rename -top gold
design -stash gold design -stash gold
read_verilog ./dynamic_part_select/multiple_blocking_gate.v read_verilog ./dynamic_part_select/multiple_blocking_gate.v
hierarchy -top multiple_blocking_gate; proc; opt; proc
prep -flatten -top multiple_blocking_gate
rename -top gate rename -top gate
design -stash gate design -stash gate
@ -35,19 +31,17 @@ design -copy-from gold -as gold gold
design -copy-from gate -as gate gate design -copy-from gate -as gate gate
miter -equiv -make_assert -make_outcmp -flatten gold gate equiv miter -equiv -make_assert -make_outcmp -flatten gold gate equiv
hierarchy -top equiv
sat -prove-asserts -seq 10 -show-public -verify -set-init-zero -ignore_unknown_cells equiv sat -prove-asserts -seq 10 -show-public -verify -set-init-zero -ignore_unknown_cells equiv
### Non-blocking to the same output register ### ### Non-blocking to the same output register ###
design -reset
read_verilog ./dynamic_part_select/nonblocking.v read_verilog ./dynamic_part_select/nonblocking.v
hierarchy -top nonblocking; proc; opt; proc
prep -flatten -top nonblocking
rename -top gold rename -top gold
design -stash gold design -stash gold
read_verilog ./dynamic_part_select/nonblocking_gate.v read_verilog ./dynamic_part_select/nonblocking_gate.v
hierarchy -top nonblocking_gate; proc; opt; proc
prep -flatten -top nonblocking_gate
rename -top gate rename -top gate
design -stash gate design -stash gate
@ -55,19 +49,17 @@ design -copy-from gold -as gold gold
design -copy-from gate -as gate gate design -copy-from gate -as gate gate
miter -equiv -make_assert -make_outcmp -flatten gold gate equiv miter -equiv -make_assert -make_outcmp -flatten gold gate equiv
hierarchy -top equiv
sat -prove-asserts -seq 10 -show-public -verify -set-init-zero -ignore_unknown_cells equiv sat -prove-asserts -seq 10 -show-public -verify -set-init-zero -ignore_unknown_cells equiv
### For-loop select, one dynamic input ### For-loop select, one dynamic input
design -reset
read_verilog ./dynamic_part_select/forloop_select.v read_verilog ./dynamic_part_select/forloop_select.v
hierarchy -top forloop_select; proc; opt; proc
prep -flatten -top forloop_select
rename -top gold rename -top gold
design -stash gold design -stash gold
read_verilog ./dynamic_part_select/forloop_select_gate.v read_verilog ./dynamic_part_select/forloop_select_gate.v
hierarchy -top forloop_select_gate; proc; opt; proc
prep -flatten -top forloop_select_gate
rename -top gate rename -top gate
design -stash gate design -stash gate
@ -75,19 +67,17 @@ design -copy-from gold -as gold gold
design -copy-from gate -as gate gate design -copy-from gate -as gate gate
miter -equiv -make_assert -make_outcmp -flatten gold gate equiv miter -equiv -make_assert -make_outcmp -flatten gold gate equiv
hierarchy -top equiv
sat -prove-asserts -seq 10 -show-public -verify -set-init-zero -ignore_unknown_cells equiv sat -prove-asserts -seq 10 -show-public -verify -set-init-zero -ignore_unknown_cells equiv
#### Double loop (part-select, reset) ### #### Double loop (part-select, reset) ###
design -reset
read_verilog ./dynamic_part_select/reset_test.v read_verilog ./dynamic_part_select/reset_test.v
hierarchy -top reset_test; proc; opt; proc
prep -flatten -top reset_test
rename -top gold rename -top gold
design -stash gold design -stash gold
read_verilog ./dynamic_part_select/reset_test_gate.v read_verilog ./dynamic_part_select/reset_test_gate.v
hierarchy -top reset_test_gate; proc; opt; proc
prep -flatten -top reset_test_gate
rename -top gate rename -top gate
design -stash gate design -stash gate
@ -95,19 +85,17 @@ design -copy-from gold -as gold gold
design -copy-from gate -as gate gate design -copy-from gate -as gate gate
miter -equiv -make_assert -make_outcmp -flatten gold gate equiv miter -equiv -make_assert -make_outcmp -flatten gold gate equiv
hierarchy -top equiv
sat -prove-asserts -seq 10 -show-public -verify -set-init-zero -ignore_unknown_cells equiv sat -prove-asserts -seq 10 -show-public -verify -set-init-zero -ignore_unknown_cells equiv
### Reversed part-select case ### ### Reversed part-select case ###
design -reset
read_verilog ./dynamic_part_select/reversed.v read_verilog ./dynamic_part_select/reversed.v
hierarchy -top reversed; proc; opt; proc
prep -flatten -top reversed
rename -top gold rename -top gold
design -stash gold design -stash gold
read_verilog ./dynamic_part_select/reversed_gate.v read_verilog ./dynamic_part_select/reversed_gate.v
hierarchy -top reversed_gate; proc; opt; proc
prep -flatten -top reversed_gate
rename -top gate rename -top gate
design -stash gate design -stash gate
@ -115,5 +103,4 @@ design -copy-from gold -as gold gold
design -copy-from gate -as gate gate design -copy-from gate -as gate gate
miter -equiv -make_assert -make_outcmp -flatten gold gate equiv miter -equiv -make_assert -make_outcmp -flatten gold gate equiv
hierarchy -top equiv
sat -prove-asserts -seq 10 -show-public -verify -set-init-zero -ignore_unknown_cells equiv sat -prove-asserts -seq 10 -show-public -verify -set-init-zero -ignore_unknown_cells equiv