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Use Verific hier_tree component for elaboration

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Clifford Wolf 2018-03-08 13:26:33 +01:00
parent 8b604004da
commit a15208f301
2 changed files with 55 additions and 1 deletions
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Makefile
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@ -279,7 +279,7 @@ endif
ifeq ($(ENABLE_VERIFIC),1)
VERIFIC_DIR ?= /usr/local/src/verific_lib_eval
VERIFIC_COMPONENTS ?= verilog vhdl database util containers sdf
VERIFIC_COMPONENTS ?= verilog vhdl database util containers sdf hier_tree
CXXFLAGS += $(patsubst %,-I$(VERIFIC_DIR)/%,$(VERIFIC_COMPONENTS)) -DYOSYS_ENABLE_VERIFIC
LDLIBS += $(patsubst %,$(VERIFIC_DIR)/%/*-linux.a,$(VERIFIC_COMPONENTS)) -lz
endif