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docs/source/appendix/APPNOTE_012_Verilog_to_BTOR.rst
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docs/source/appendix/APPNOTE_012_Verilog_to_BTOR.rst
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====================================
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012: Converting Verilog to BTOR page
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====================================
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Installation
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============
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Yosys written in C++ (using features from C++11) and is tested on modern Linux.
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It should compile fine on most UNIX systems with a C++11 compiler. The README
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file contains useful information on building Yosys and its prerequisites.
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Yosys is a large and feature-rich program with some dependencies. For this work,
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we may deactivate other extra features such as TCL and ABC support in the
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Makefile.
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This Application Note is based on `Yosys GIT`_ `Rev. 082550f` from 2015-04-04.
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.. _Yosys GIT: https://github.com/YosysHQ/yosys
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.. _Rev. 082550f: https://github.com/YosysHQ/yosys/tree/082550f
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Quick start
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===========
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We assume that the Verilog design is synthesizable and we also assume that the
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design does not have multi-dimensional memories. As BTOR implicitly initializes
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registers to zero value and memories stay uninitialized, we assume that the
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Verilog design does not contain initial blocks. For more details about the BTOR
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format, please refer to :cite:p:`btor`.
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We provide a shell script ``verilog2btor.sh`` which can be used to convert a
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Verilog design to BTOR. The script can be found in the ``backends/btor``
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directory. The following example shows its usage:
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.. code:: sh
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verilog2btor.sh fsm.v fsm.btor test
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The script ``verilog2btor.sh`` takes three parameters. In the above example, the
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first parameter ``fsm.v`` is the input design, the second parameter ``fsm.btor``
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is the file name of BTOR output, and the third parameter ``test`` is the name of
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top module in the design.
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To specify the properties (that need to be checked), we have two
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options:
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- We can use the Verilog ``assert`` statement in the procedural block or module
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body of the Verilog design, as shown in :numref:`specifying_property_assert`.
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This is the preferred option.
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- We can use a single-bit output wire, whose name starts with ``safety``. The
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value of this output wire needs to be driven low when the property is met,
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i.e. the solver will try to find a model that makes the safety pin go high.
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This is demonstrated in :numref:`specifying_property_output`.
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.. code-block:: verilog
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:caption: Specifying property in Verilog design with ``assert``
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:name: specifying_property_assert
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module test(input clk, input rst, output y);
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reg [2:0] state;
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always @(posedge clk) begin
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if (rst || state == 3) begin
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state <= 0;
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end else begin
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assert(state < 3);
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state <= state + 1;
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end
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end
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assign y = state[2];
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assert property (y !== 1'b1);
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endmodule
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.. code-block:: verilog
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:caption: Specifying property in Verilog design with output wire
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:name: specifying_property_output
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module test(input clk, input rst,
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output y, output safety1);
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reg [2:0] state;
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always @(posedge clk) begin
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if (rst || state == 3)
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state <= 0;
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else
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state <= state + 1;
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end
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assign y = state[2];
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assign safety1 = !(y !== 1'b1);
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endmodule
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We can run `Boolector`_ ``1.4.1`` [1]_ on the generated BTOR file:
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.. _Boolector: http://fmv.jku.at/boolector/
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.. code:: sh
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$ boolector fsm.btor
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unsat
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We can also use `nuXmv`_, but on BTOR designs it does not support memories yet.
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With the next release of nuXmv, we will be also able to verify designs with
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memories.
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.. _nuXmv: https://es-static.fbk.eu/tools/nuxmv/index.php
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Detailed flow
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=============
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Yosys is able to synthesize Verilog designs up to the gate level. We are
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interested in keeping registers and memories when synthesizing the design. For
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this purpose, we describe a customized Yosys synthesis flow, that is also
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provided by the ``verilog2btor.sh`` script. :numref:`btor_script_memory` shows
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the Yosys commands that are executed by ``verilog2btor.sh``.
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.. code-block:: yoscrypt
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:caption: Synthesis Flow for BTOR with memories
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:name: btor_script_memory
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read_verilog -sv $1;
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hierarchy -top $3; hierarchy -libdir $DIR;
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hierarchy -check;
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proc; opt;
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opt_expr -mux_undef; opt;
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rename -hide;;;
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splice; opt;
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memory_dff -wr_only; memory_collect;;
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flatten;;
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memory_unpack;
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splitnets -driver;
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setundef -zero -undriven;
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opt;;;
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write_btor $2;
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Here is short description of what is happening in the script line by
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line:
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#. Reading the input file.
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#. Setting the top module in the hierarchy and trying to read automatically the
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files which are given as ``include`` in the file read in first line.
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#. Checking the design hierarchy.
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#. Converting processes to multiplexers (muxs) and flip-flops.
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#. Removing undef signals from muxs.
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#. Hiding all signal names that are not used as module ports.
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#. Explicit type conversion, by introducing slice and concat cells in the
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circuit.
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#. Converting write memories to synchronous memories, and collecting the
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memories to multi-port memories.
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#. Flattening the design to get only one module.
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#. Separating read and write memories.
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#. Splitting the signals that are partially assigned
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#. Setting undef to zero value.
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#. Final optimization pass.
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#. Writing BTOR file.
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For detailed description of the commands mentioned above, please refer
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to the Yosys documentation, or run ``yosys -h <command_name>``.
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The script presented earlier can be easily modified to have a BTOR file that
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does not contain memories. This is done by removing the line number 8 and 10,
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and introduces a new command ``memory`` at line number 8.
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:numref:`btor_script_without_memory` shows the modified Yosys script file:
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.. code-block:: sh
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:caption: Synthesis Flow for BTOR without memories
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:name: btor_script_without_memory
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read_verilog -sv $1;
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hierarchy -top $3; hierarchy -libdir $DIR;
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hierarchy -check;
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proc; opt;
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opt_expr -mux_undef; opt;
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rename -hide;;;
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splice; opt;
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memory;;
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flatten;;
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splitnets -driver;
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setundef -zero -undriven;
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opt;;;
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write_btor $2;
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Example
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=======
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Here is an example Verilog design that we want to convert to BTOR:
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.. code-block:: verilog
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:caption: Example - Verilog Design
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:name: example_verilog
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module array(input clk);
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reg [7:0] counter;
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reg [7:0] mem [7:0];
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always @(posedge clk) begin
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counter <= counter + 8'd1;
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mem[counter] <= counter;
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end
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assert property (!(counter > 8'd0) ||
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mem[counter - 8'd1] == counter - 8'd1);
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endmodule
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The generated BTOR file that contain memories, using the script shown in
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:numref:`btor_memory`:
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.. code-block::
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:caption: Example - Converted BTOR with memory
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:name: btor_memory
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1 var 1 clk
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2 array 8 3
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3 var 8 $auto$rename.cc:150:execute$20
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4 const 8 00000001
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5 sub 8 3 4
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6 slice 3 5 2 0
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7 read 8 2 6
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8 slice 3 3 2 0
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9 add 8 3 4
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10 const 8 00000000
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11 ugt 1 3 10
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12 not 1 11
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13 const 8 11111111
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14 slice 1 13 0 0
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15 one 1
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16 eq 1 1 15
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17 and 1 16 14
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18 write 8 3 2 8 3
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19 acond 8 3 17 18 2
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20 anext 8 3 2 19
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21 eq 1 7 5
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22 or 1 12 21
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23 const 1 1
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24 one 1
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25 eq 1 23 24
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26 cond 1 25 22 24
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27 root 1 -26
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28 cond 8 1 9 3
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29 next 8 3 28
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And the BTOR file obtained by the script shown in
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:numref:`btor_without_memory`, which expands the memory into individual
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elements:
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.. code-block::
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:caption: Example - Converted BTOR with memory
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:name: btor_without_memory
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1 var 1 clk
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2 var 8 mem[0]
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3 var 8 $auto$rename.cc:150:execute$20
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4 slice 3 3 2 0
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5 slice 1 4 0 0
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6 not 1 5
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7 slice 1 4 1 1
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8 not 1 7
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9 slice 1 4 2 2
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10 not 1 9
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11 and 1 8 10
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12 and 1 6 11
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13 cond 8 12 3 2
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14 cond 8 1 13 2
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15 next 8 2 14
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16 const 8 00000001
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17 add 8 3 16
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18 const 8 00000000
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19 ugt 1 3 18
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20 not 1 19
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21 var 8 mem[2]
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22 and 1 7 10
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23 and 1 6 22
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24 cond 8 23 3 21
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25 cond 8 1 24 21
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26 next 8 21 25
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27 sub 8 3 16
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...
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54 cond 1 53 50 52
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55 root 1 -54
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...
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77 cond 8 76 3 44
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78 cond 8 1 77 44
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79 next 8 44 78
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Limitations
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===========
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BTOR does not support initialization of memories and registers, i.e. they are
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implicitly initialized to value zero, so the initial block for memories need to
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be removed when converting to BTOR. It should also be kept in consideration that
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BTOR does not support the ``x`` or ``z`` values of Verilog.
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Another thing to bear in mind is that Yosys will convert multi-dimensional
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memories to one-dimensional memories and address decoders. Therefore
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out-of-bounds memory accesses can yield unexpected results.
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Conclusion
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==========
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Using the described flow, we can use Yosys to generate word-level verification
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benchmarks with or without memories from Verilog designs.
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.. [1]
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Newer version of Boolector do not support sequential models.
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Boolector 1.4.1 can be built with picosat-951. Newer versions of
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picosat have an incompatible API.
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