mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-22 15:34:36 +00:00
Code Activity

analogdevices: LUT RAM only on positive edge

Browse source
This commit is contained in:
Lofty 2025-10-18 12:11:18 +01:00
parent f1579304a6
commit a119711aac
1 changed files with 1 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

2
techlibs/analogdevices/lutrams.txt
View file

@ -13,7 +13,7 @@ ram distributed $__ANALOGDEVICES_LUTRAM_SP_ {
init no_undef; init no_undef;
prune_rom; prune_rom;
port arsw "RW" { port arsw "RW" {
clock anyedge; clock posedge;
} }
} }