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This commit is contained in:
Akash Levy 2024-10-01 04:13:01 -07:00
parent 3b8bc8098f
commit a0ebd9545a
2 changed files with 8 additions and 1 deletions
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7
Makefile
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@ -8,6 +8,9 @@ CONFIG := none
# CONFIG := msys2-32 # CONFIG := msys2-32
# CONFIG := msys2-64 # CONFIG := msys2-64
# silimate
DISABLE_MEM_PRIORITY_MASK := 1 # not logically equivalent!
# features (the more the better) # features (the more the better)
ENABLE_TCL := 0 ENABLE_TCL := 0
ENABLE_ABC := 0 ENABLE_ABC := 0
@ -488,6 +491,10 @@ endif
endif endif
endif endif
ifeq ($(DISABLE_MEM_PRIORITY_MASK),1)
CXXFLAGS += -DSILIMATE_DISABLE_MEM_PRIORITY_MASK
endif
ifeq ($(ENABLE_GHDL),1) ifeq ($(ENABLE_GHDL),1)
GHDL_PREFIX ?= $(PREFIX) GHDL_PREFIX ?= $(PREFIX)
GHDL_INCLUDE_DIR ?= $(GHDL_PREFIX)/include GHDL_INCLUDE_DIR ?= $(GHDL_PREFIX)/include

2
kernel/mem.cc
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@ -782,7 +782,7 @@ namespace {
mwr.en = cell->getPort(ID::WR_EN).extract(i * res.width, (ni - i) * res.width); mwr.en = cell->getPort(ID::WR_EN).extract(i * res.width, (ni - i) * res.width);
mwr.addr = cell->getPort(ID::WR_ADDR).extract(i * abits, abits); mwr.addr = cell->getPort(ID::WR_ADDR).extract(i * abits, abits);
mwr.data = cell->getPort(ID::WR_DATA).extract(i * res.width, (ni - i) * res.width); mwr.data = cell->getPort(ID::WR_DATA).extract(i * res.width, (ni - i) * res.width);
#ifndef ENABLE_VERIFIC_SYSTEMVERILOG #ifndef SILIMATE_DISABLE_MEM_PRIORITY_MASK
if (!is_compat) { if (!is_compat) {
Const priority_mask = cell->parameters.at(ID::WR_PRIORITY_MASK).extract(i * n_wr_ports, n_wr_ports); Const priority_mask = cell->parameters.at(ID::WR_PRIORITY_MASK).extract(i * n_wr_ports, n_wr_ports);
for (int j = 0; j < n_wr_ports; j++) for (int j = 0; j < n_wr_ports; j++)