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Add extra test

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Kelvin Chung 2025-03-26 22:24:41 +00:00
parent 7bbdf6049a
commit a0dabf9203
1 changed files with 9 additions and 0 deletions
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9
tests/techmap/constmap.ys
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@ -13,6 +13,13 @@ select -assert-count 1 t:const_cell
select -assert-count 1 r:value=16 select -assert-count 1 r:value=16
design -reset design -reset
read_verilog -lib << EOT
module const_cell(O);
output O;
endmodule
EOT
read_verilog << EOT read_verilog << EOT
module test(); module test();
@ -29,3 +36,5 @@ constmap -cell const_cell O value
select -assert-count 2 t:const_cell select -assert-count 2 t:const_cell
select -assert-count 1 r:value=16 select -assert-count 1 r:value=16
select -assert-count 1 r:value=32 select -assert-count 1 r:value=32
select -assert-count 1 test/out1 %ci* r:value=16 %i
select -assert-count 1 test/out2 %ci* r:value=32 %i