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simplemap: Autogenerate the help

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Martin Povišer 2024-07-25 11:41:42 +02:00
parent e621e9b761
commit a0ab6ad7b0
1 changed files with 4 additions and 5 deletions
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9
passes/techmap/simplemap.cc
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@ -478,11 +478,10 @@ struct SimplemapPass : public Pass {
log("This pass maps a small selection of simple coarse-grain cells to yosys gate\n"); log("This pass maps a small selection of simple coarse-grain cells to yosys gate\n");
log("primitives. The following internal cell types are mapped by this pass:\n"); log("primitives. The following internal cell types are mapped by this pass:\n");
log("\n"); log("\n");
log(" $not, $pos, $and, $or, $xor, $xnor\n"); dict<IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> mappers;
log(" $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor, $reduce_bool\n"); simplemap_get_mappers(mappers);
log(" $logic_not, $logic_and, $logic_or, $mux, $tribuf\n"); for (auto pair : mappers)
log(" $sr, $ff, $dff, $dffe, $dffsr, $dffsre, $adff, $adffe, $aldff, $aldffe, $sdff,\n"); log(" - %s\n", log_id(pair.first));
log(" $sdffe, $sdffce, $dlatch, $adlatch, $dlatchsr\n");
log("\n"); log("\n");
} }
void execute(std::vector<std::string> args, RTLIL::Design *design) override void execute(std::vector<std::string> args, RTLIL::Design *design) override