From a0ab6ad7b088337a9990c655ca93bcf0f10ef695 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Thu, 25 Jul 2024 11:41:42 +0200 Subject: [PATCH] simplemap: Autogenerate the help --- passes/techmap/simplemap.cc | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index ab247a6d7..a7bc7ac15 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -478,11 +478,10 @@ struct SimplemapPass : public Pass { log("This pass maps a small selection of simple coarse-grain cells to yosys gate\n"); log("primitives. The following internal cell types are mapped by this pass:\n"); log("\n"); - log(" $not, $pos, $and, $or, $xor, $xnor\n"); - log(" $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor, $reduce_bool\n"); - log(" $logic_not, $logic_and, $logic_or, $mux, $tribuf\n"); - log(" $sr, $ff, $dff, $dffe, $dffsr, $dffsre, $adff, $adffe, $aldff, $aldffe, $sdff,\n"); - log(" $sdffe, $sdffce, $dlatch, $adlatch, $dlatchsr\n"); + dict mappers; + simplemap_get_mappers(mappers); + for (auto pair : mappers) + log(" - %s\n", log_id(pair.first)); log("\n"); } void execute(std::vector args, RTLIL::Design *design) override