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Fine tune xilinx_dsp pattern matcher

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This commit is contained in:
Eddie Hung 2019-08-30 16:18:58 -07:00
parent 9be9631e5a
commit a09e69dd56
1 changed files with 18 additions and 14 deletions
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32
passes/pmgen/xilinx_dsp.pmg
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@ -76,8 +76,9 @@ match ffM
select param(ffM, \CLK_POLARITY).as_bool() select param(ffM, \CLK_POLARITY).as_bool()
select nusers(port(ffM, \D)) == 2 select nusers(port(ffM, \D)) == 2
//index <SigSpec> port(ffM, \D) === sigM.extract(0, GetSize(port(ffM, \D))) // TODO: Why doesn't this work!?! //index <SigSpec> port(ffM, \D) === sigM.extract(0, GetSize(port(ffM, \D))) // TODO: Why doesn't this work!?!
filter GetSize(port(ffM, \D)) <= GetSize(sigM)
filter port(ffM, \D) == sigM.extract(0, GetSize(port(ffM, \D))) filter port(ffM, \D) == sigM.extract(0, GetSize(port(ffM, \D)))
filter nusers(sigM.extract_end(param(ffM, \WIDTH).as_int())) == 1 filter nusers(sigM.extract_end(GetSize(port(ffM, \D)))) <= 1
optional optional
endmatch endmatch
@ -88,7 +89,7 @@ code clock sigM sigP
if (b.wire->get_bool_attribute(\keep)) if (b.wire->get_bool_attribute(\keep))
reject; reject;
SigBit c = port(ffB, \CLK).as_bit(); SigBit c = port(ffM, \CLK).as_bit();
if (clock != SigBit() && c != clock) if (clock != SigBit() && c != clock)
reject; reject;
@ -102,10 +103,11 @@ endcode
match addA match addA
select addA->type.in($add) select addA->type.in($add)
select param(addA, \A_SIGNED).as_bool() && param(addA, \B_SIGNED).as_bool() select param(addA, \A_SIGNED).as_bool() && param(addA, \B_SIGNED).as_bool()
index <int> nusers(port(addA, \A)) === 2 select nusers(port(addA, \A)) == 2
//index <SigSpec> port(addA, \A) === sigP.extract(0, param(addA, \A_WIDTH).as_int()) //index <SigSpec> port(addA, \A) === sigP.extract(0, param(addA, \A_WIDTH).as_int()) // TODO: Why doesn't this work!?!
filter param(addA, \A_WIDTH).as_int() <= GetSize(sigP) filter GetSize(port(addA, \A)) <= GetSize(sigP)
filter port(addA, \A) == sigP.extract(0, param(addA, \A_WIDTH).as_int()) filter port(addA, \A) == sigP.extract(0, GetSize(port(addA, \A)))
filter nusers(sigP.extract_end(GetSize(port(addA, \A)))) <= 1
optional optional
endmatch endmatch
@ -114,9 +116,10 @@ match addB
select addB->type.in($add, $sub) select addB->type.in($add, $sub)
select param(addB, \A_SIGNED).as_bool() && param(addB, \B_SIGNED).as_bool() select param(addB, \A_SIGNED).as_bool() && param(addB, \B_SIGNED).as_bool()
index <int> nusers(port(addB, \B)) === 2 index <int> nusers(port(addB, \B)) === 2
//index <SigSpec> port(addB, \B) === sigP.extract(0, param(addB, \B_WIDTH).as_int()) //index <SigSpec> port(addB, \B) === sigP.extract(0, param(addB, \B_WIDTH).as_int()) // TODO: Why doesn't this work!?!
filter param(addB, \B_WIDTH).as_int() <= GetSize(sigP) filter GetSize(port(addB, \B)) <= GetSize(sigP)
filter port(addB, \B) == sigP.extract(0, param(addB, \B_WIDTH).as_int()) filter port(addB, \B) == sigP.extract(0, GetSize(port(addB, \B)))
filter nusers(sigP.extract_end(GetSize(port(addB, \B)))) <= 1
optional optional
endmatch endmatch
@ -135,12 +138,13 @@ code addAB sigC sigP
if (!opmodeZ.is_fully_zero()) if (!opmodeZ.is_fully_zero())
reject; reject;
int natural_mul_width = GetSize(port(dsp, \A)) + GetSize(port(dsp, \B)); // TODO for DSP48E1, which will have sign extended inputs/outputs
int actual_mul_width = GetSize(sigP); //int natural_mul_width = GetSize(port(dsp, \A)) + GetSize(port(dsp, \B));
int actual_acc_width = GetSize(sigC); //int actual_mul_width = GetSize(sigP);
//int actual_acc_width = GetSize(sigC);
if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width)) //if ((actual_acc_width > actual_mul_width) && (natural_mul_width > actual_mul_width))
reject; // reject;
//if ((actual_acc_width != actual_mul_width) && (param(dsp, \A_SIGNED).as_bool() != param(addAB, \A_SIGNED).as_bool())) //if ((actual_acc_width != actual_mul_width) && (param(dsp, \A_SIGNED).as_bool() != param(addAB, \A_SIGNED).as_bool()))
// reject; // reject;