mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-13 12:28:44 +00:00
Code Activity

Merge pull request #1401 from SergeyDegtyar/SergeyDegtyar/ice40

Browse source 
ICE40 tests. adffs test update (equiv_opt -multiclock).
This commit is contained in:
Eddie Hung 2019-09-25 16:43:24 -07:00 committed by GitHub
parent 739c621330 b66364ada2
commit a009314597
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
2 changed files with 14 additions and 19 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

20
tests/ice40/adffs.v
View file

@ -22,29 +22,25 @@ module adffn
q <= d; q <= d;
endmodule endmodule
module dffsr module dffs
( input d, clk, pre, clr, output reg q ); ( input d, clk, pre, clr, output reg q );
initial begin initial begin
q = 0; q = 0;
end end
always @( posedge clk, posedge pre, posedge clr ) always @( posedge clk, posedge pre )
if ( clr ) if ( pre )
q <= 1'b0;
else if ( pre )
q <= 1'b1; q <= 1'b1;
else else
q <= d; q <= d;
endmodule endmodule
module ndffnsnr module ndffnr
( input d, clk, pre, clr, output reg q ); ( input d, clk, pre, clr, output reg q );
initial begin initial begin
q = 0; q = 0;
end end
always @( negedge clk, negedge pre, negedge clr ) always @( negedge clk, negedge pre )
if ( !clr ) if ( !pre )
q <= 1'b0;
else if ( !pre )
q <= 1'b1; q <= 1'b1;
else else
q <= d; q <= d;
@ -58,7 +54,7 @@ input a,
output b,b1,b2,b3 output b,b1,b2,b3
); );
dffsr u_dffsr ( dffs u_dffs (
.clk (clk ), .clk (clk ),
.clr (clr), .clr (clr),
.pre (pre), .pre (pre),
@ -66,7 +62,7 @@ dffsr u_dffsr (
.q (b ) .q (b )
); );
ndffnsnr u_ndffnsnr ( ndffnr u_ndffnr (
.clk (clk ), .clk (clk ),
.clr (clr), .clr (clr),
.pre (pre), .pre (pre),

13
tests/ice40/adffs.ys
View file

@ -1,12 +1,11 @@
read_verilog adffs.v read_verilog adffs.v
proc proc
async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock
flatten flatten
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check equiv_opt -multiclock -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:SB_DFF select -assert-count 1 t:SB_DFFNS
select -assert-count 1 t:SB_DFFN select -assert-count 2 t:SB_DFFR
select -assert-count 2 t:SB_DFFSR select -assert-count 1 t:SB_DFFS
select -assert-count 7 t:SB_LUT4 select -assert-count 2 t:SB_LUT4
select -assert-none t:SB_DFF t:SB_DFFN t:SB_DFFSR t:SB_LUT4 %% t:* %D select -assert-none t:SB_DFFNS t:SB_DFFR t:SB_DFFS t:SB_LUT4 %% t:* %D