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Panic over. Model was elsewhere. Re-arrange for consistency

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This commit is contained in:
Eddie Hung 2019-10-04 10:48:44 -07:00
parent 4e11782cde
commit 9fef1df3c1
5 changed files with 4 additions and 31 deletions
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3
techlibs/ice40/synth_ice40.cc
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@ -245,7 +245,7 @@ struct SynthIce40Pass : public ScriptPass
define = "-D ICE40_U";
else
define = "-D ICE40_HX";
run("read_verilog -icells " + define + " -lib +/ice40/cells_sim.v");
run("read_verilog " + define + " -lib +/ice40/cells_sim.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
run("proc");
}
@ -349,6 +349,7 @@ struct SynthIce40Pass : public ScriptPass
}
if (!noabc) {
if (abc == "abc9") {
run("read_verilog -icells -lib +/ice40/abc_model.v");
int wire_delay;
if (device_opt == "lp")
wire_delay = 400;