mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-08 17:01:57 +00:00
Code Activity

memory_dff: Recognize soft transparency logic.

Browse source
This commit is contained in:
Marcelina Kościelnicka 2021-08-10 19:42:10 +02:00
parent 616ace2d92
commit 9fdedf4d1c
4 changed files with 1355 additions and 7 deletions
Download patch file Download diff file Expand all files Collapse all files

21
tests/memories/trans_sdp.v Normal file
View file

@ -0,0 +1,21 @@
// expect-wr-ports 1
// expect-rd-ports 1
// expect-rd-clk \clk
// expect-rd-en \re
module top(input clk, we, re, input [7:0] ra, wa, wd, output reg [7:0] rd);
reg [7:0] mem[0:255];
always @(posedge clk) begin
if (we)
mem[wa] <= wd;
if (re) begin
rd <= mem[ra];
if (we && ra == wa)
rd <= wd;
end
end
endmodule

21
tests/memories/trans_sp.v Normal file
View file

@ -0,0 +1,21 @@
// expect-wr-ports 1
// expect-rd-ports 1
// expect-rd-clk \clk
// expect-rd-en \re
module top(input clk, we, re, input [7:0] addr, wd, output reg [7:0] rd);
reg [7:0] mem[0:255];
always @(posedge clk) begin
if (we)
mem[addr] <= wd;
if (re) begin
rd <= mem[addr];
if (we)
rd <= wd;
end
end
endmodule