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Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9

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Rename abc_* names/attributes to more precisely be abc9_*
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Eddie Hung 2019-10-08 10:53:38 -07:00 • committed by GitHub
commit 9fd2ddb14c
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34 changed files with 316 additions and 309 deletions
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15
techlibs/xilinx/synth_xilinx.cc
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@ -478,16 +478,17 @@ struct SynthXilinxPass : public ScriptPass
run("abc -luts 2:2,3,6:5[,10,20] [-dff]", "(option for 'nowidelut'; option for '-retime')");
else if (abc9) {
if (family != "xc7")
log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n");
run("techmap -map +/xilinx/abc_map.v -max_iter 1");
run("read_verilog -icells -lib +/xilinx/abc_model.v");
std::string abc9_opts = " -box +/xilinx/abc_xc7.box";
log_warning("'synth_xilinx -abc9' not currently supported for the '%s' family, "
"will use timing for 'xc7' instead.\n", family.c_str());
run("techmap -map +/xilinx/abc9_map.v -max_iter 1");
run("read_verilog -icells -lib +/xilinx/abc9_model.v");
std::string abc9_opts = " -box +/xilinx/abc9_xc7.box";
abc9_opts += stringf(" -W %d", XC7_WIRE_DELAY);
abc9_opts += " -nomfs";
if (nowidelut)
abc9_opts += " -lut +/xilinx/abc_xc7_nowide.lut";
abc9_opts += " -lut +/xilinx/abc9_xc7_nowide.lut";
else
abc9_opts += " -lut +/xilinx/abc_xc7.lut";
abc9_opts += " -lut +/xilinx/abc9_xc7.lut";
run("abc9" + abc9_opts);
}
else {
@ -506,7 +507,7 @@ struct SynthXilinxPass : public ScriptPass
if (help_mode)
techmap_args += " [-map " + ff_map_file + "]";
else if (abc9)
techmap_args += " -map +/xilinx/abc_unmap.v";
techmap_args += " -map +/xilinx/abc9_unmap.v";
else
techmap_args += " -map " + ff_map_file;
run("techmap " + techmap_args);