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Merge pull request #5963 from YosysHQ/nella/latch-toggle

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User control over latch inference
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nella 2026-07-08 10:24:06 +00:00 • committed by GitHub
commit 9fc4cdbc5c
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20 changed files with 319 additions and 36 deletions
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1
docs/source/code_examples/macro_commands/synth_ice40.ys
View file

@ -67,6 +67,7 @@ map_ffs:
map_luts: map_luts:
abc abc
ice40_opt ice40_opt
check
techmap techmap
simplemap simplemap
techmap techmap

41
passes/cmds/check.cc
View file

@ -60,6 +60,15 @@ struct CheckPass : public Pass {
log(" also check for internal cells that have not been mapped to cells of the\n"); log(" also check for internal cells that have not been mapped to cells of the\n");
log(" target architecture\n"); log(" target architecture\n");
log("\n"); log("\n");
log(" -nolatches\n");
log(" also check for latch cells ($dlatch, $adlatch, $dlatchsr and their\n");
log(" $_DLATCH_*/$_DLATCHSR_* mappings) remaining in the design. Use this\n");
log(" before techmapping in flows that must not emit latches.\n");
log("\n");
log(" -latchonly\n");
log(" check only for latch cells (as listed under -nolatches), skipping all\n");
log(" other checks.\n");
log("\n");
log(" -allow-tbuf\n"); log(" -allow-tbuf\n");
log(" modify the -mapped behavior to still allow $_TBUF_ cells\n"); log(" modify the -mapped behavior to still allow $_TBUF_ cells\n");
log("\n"); log("\n");
@ -79,6 +88,8 @@ struct CheckPass : public Pass {
bool noinit = false; bool noinit = false;
bool initdrv = false; bool initdrv = false;
bool mapped = false; bool mapped = false;
bool nolatches = false;
bool latchonly = false;
bool allow_tbuf = false; bool allow_tbuf = false;
bool assert_mode = false; bool assert_mode = false;
bool force_detailed_loop_check = false; bool force_detailed_loop_check = false;
@ -98,6 +109,14 @@ struct CheckPass : public Pass {
mapped = true; mapped = true;
continue; continue;
} }
if (args[argidx] == "-nolatches") {
nolatches = true;
continue;
}
if (args[argidx] == "-latchonly") {
latchonly = true;
continue;
}
if (args[argidx] == "-allow-tbuf") { if (args[argidx] == "-allow-tbuf") {
allow_tbuf = true; allow_tbuf = true;
continue; continue;
@ -120,6 +139,19 @@ struct CheckPass : public Pass {
{ {
log("Checking module %s...\n", module); log("Checking module %s...\n", module);
// latch-only mode only flags latches, skipping the (potentially false-positive mid-flow) undriven/driver/loop checks below
if (latchonly) {
for (auto cell : module->cells())
if (
cell->type.in(ID($dlatch), ID($adlatch), ID($dlatchsr)) ||
cell->type.begins_with("$_DLATCH_") || cell->type.begins_with("$_DLATCHSR_")
) {
log_warning("Cell %s.%s is a latch of type %s.\n", module, cell, cell->type.unescape());
counter++;
}
continue;
}
SigMap sigmap(module); SigMap sigmap(module);
dict<SigBit, vector<string>> wire_drivers; dict<SigBit, vector<string>> wire_drivers;
dict<SigBit, Cell *> driver_cells; dict<SigBit, Cell *> driver_cells;
@ -265,6 +297,15 @@ struct CheckPass : public Pass {
cell_allowed:; cell_allowed:;
} }
if (
nolatches && (
cell->type.in(ID($dlatch), ID($adlatch), ID($dlatchsr)) ||
cell->type.begins_with("$_DLATCH_") || cell->type.begins_with("$_DLATCHSR_"))
) {
log_warning("Cell %s.%s is a latch of type %s.\n", module, cell, cell->type.unescape());
counter++;
}
for (auto &conn : cell->connections()) { for (auto &conn : cell->connections()) {
bool input = cell->input(conn.first); bool input = cell->input(conn.first);
bool output = cell->output(conn.first); bool output = cell->output(conn.first);

13
passes/proc/proc.cc
View file

@ -69,10 +69,14 @@ struct ProcPass : public Pass {
log(" -noopt\n"); log(" -noopt\n");
log(" Will omit the opt_expr pass.\n"); log(" Will omit the opt_expr pass.\n");
log("\n"); log("\n");
log(" -latches <auto|warn|error>\n");
log(" controls how the inference of a latch is reported.\n");
log("\n");
} }
void execute(std::vector<std::string> args, RTLIL::Design *design) override void execute(std::vector<std::string> args, RTLIL::Design *design) override
{ {
std::string global_arst; std::string global_arst;
std::string latches;
bool ifxmode = false; bool ifxmode = false;
bool nomux = false; bool nomux = false;
bool noopt = false; bool noopt = false;
@ -104,6 +108,10 @@ struct ProcPass : public Pass {
norom = true; norom = true;
continue; continue;
} }
if (args[argidx] == "-latches" && argidx+1 < args.size()) {
latches = args[++argidx];
continue;
}
break; break;
} }
extra_args(args, argidx, design); extra_args(args, argidx, design);
@ -121,7 +129,10 @@ struct ProcPass : public Pass {
Pass::call(design, "proc_rom"); Pass::call(design, "proc_rom");
if (!nomux) if (!nomux)
Pass::call(design, ifxmode ? "proc_mux -ifx" : "proc_mux"); Pass::call(design, ifxmode ? "proc_mux -ifx" : "proc_mux");
Pass::call(design, "proc_dlatch"); if (latches.empty())
Pass::call(design, "proc_dlatch");
else
Pass::call(design, "proc_dlatch -latches " + latches);
Pass::call(design, "proc_dff"); Pass::call(design, "proc_dff");
Pass::call(design, "proc_memwr"); Pass::call(design, "proc_memwr");
Pass::call(design, "proc_clean"); Pass::call(design, "proc_clean");

47
passes/proc/proc_dlatch.cc
View file

@ -416,7 +416,13 @@ struct proc_dlatch_db_t
} }
}; };
void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc) enum LatchPolicy {
POLICY_INFO,
POLICY_WARN,
POLICY_ERROR
};
void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc, LatchPolicy policy)
{ {
RTLIL::SigSig latches_bits, nolatches_bits; RTLIL::SigSig latches_bits, nolatches_bits;
dict<SigBit, SigBit> latches_out_in; dict<SigBit, SigBit> latches_out_in;
@ -545,6 +551,12 @@ void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc)
if (proc->get_bool_attribute(ID::always_comb)) if (proc->get_bool_attribute(ID::always_comb))
log_error("Latch inferred for signal `%s.%s' from always_comb process `%s.%s'.\n", log_error("Latch inferred for signal `%s.%s' from always_comb process `%s.%s'.\n",
db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str()); db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str());
else if (policy == POLICY_ERROR)
log_error("Latch inferred for signal `%s.%s' from process `%s.%s': %s\n",
db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str(), cell);
else if (policy == POLICY_WARN)
log_warning("Latch inferred for signal `%s.%s' from process `%s.%s': %s\n",
db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str(), cell);
else else
log("Latch inferred for signal `%s.%s' from process `%s.%s': %s\n", log("Latch inferred for signal `%s.%s' from process `%s.%s': %s\n",
db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str(), cell); db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str(), cell);
@ -560,22 +572,49 @@ struct ProcDlatchPass : public Pass {
{ {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n"); log("\n");
log(" proc_dlatch [selection]\n"); log(" proc_dlatch [options] [selection]\n");
log("\n"); log("\n");
log("This pass identifies latches in the processes and converts them to\n"); log("This pass identifies latches in the processes and converts them to\n");
log("d-type latches.\n"); log("d-type latches.\n");
log("\n"); log("\n");
log(" -latches <info|warn|error>\n");
log(" controls how the inference of a latch is reported. Alternatively, one\n");
log(" can use the 'proc.latches' scratchpad variable. Defaults to 'warn'.\n");
log("\n");
} }
void execute(std::vector<std::string> args, RTLIL::Design *design) override void execute(std::vector<std::string> args, RTLIL::Design *design) override
{ {
log_header(design, "Executing PROC_DLATCH pass (convert process syncs to latches).\n"); log_header(design, "Executing PROC_DLATCH pass (convert process syncs to latches).\n");
extra_args(args, 1, design); std::string policy_str;
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
if (args[argidx] == "-latches" && argidx+1 < args.size()) {
policy_str = args[++argidx];
continue;
}
break;
}
extra_args(args, argidx, design);
if (policy_str.empty())
policy_str = design->scratchpad_get_string("proc.latches", "warn");
LatchPolicy policy;
if (policy_str == "info")
policy = POLICY_INFO;
else if (policy_str == "warn")
policy = POLICY_WARN;
else if (policy_str == "error")
policy = POLICY_ERROR;
else
log_cmd_error("Invalid value '%s' for -latches (expected info|warn|error).\n", policy_str.c_str());
for (auto mod : design->all_selected_modules()) { for (auto mod : design->all_selected_modules()) {
proc_dlatch_db_t db(mod); proc_dlatch_db_t db(mod);
for (auto proc : mod->selected_processes()) for (auto proc : mod->selected_processes())
proc_dlatch(db, proc); proc_dlatch(db, proc, policy);
db.fixup_muxes(); db.fixup_muxes();
} }
} }

12
techlibs/common/synth.cc
View file

@ -78,6 +78,9 @@ struct SynthPass : public ScriptPass {
log(" -nordff\n"); log(" -nordff\n");
log(" passed to 'memory'. prohibits merging of FFs into memory read ports\n"); log(" passed to 'memory'. prohibits merging of FFs into memory read ports\n");
log("\n"); log("\n");
log(" -latches <auto|warn|error>\n");
log(" controls how the inference of a latch is reported.\n");
log("\n");
log(" -noshare\n"); log(" -noshare\n");
log(" do not run SAT-based resource sharing\n"); log(" do not run SAT-based resource sharing\n");
log("\n"); log("\n");
@ -111,7 +114,7 @@ struct SynthPass : public ScriptPass {
log("\n"); log("\n");
} }
string top_module, fsm_opts, memory_opts, abc; string top_module, fsm_opts, memory_opts, abc, latches_opt;
bool autotop, flatten, noalumacc, nofsm, noabc, noshare, flowmap, booth, arith_tree, hieropt, relative_share; bool autotop, flatten, noalumacc, nofsm, noabc, noshare, flowmap, booth, arith_tree, hieropt, relative_share;
int lut; int lut;
std::vector<std::string> techmap_maps; std::vector<std::string> techmap_maps;
@ -121,6 +124,7 @@ struct SynthPass : public ScriptPass {
top_module.clear(); top_module.clear();
fsm_opts.clear(); fsm_opts.clear();
memory_opts.clear(); memory_opts.clear();
latches_opt.clear();
autotop = false; autotop = false;
flatten = false; flatten = false;
@ -200,6 +204,10 @@ struct SynthPass : public ScriptPass {
memory_opts += " -nordff"; memory_opts += " -nordff";
continue; continue;
} }
if (args[argidx] == "-latches" && argidx + 1 < args.size()) {
latches_opt += " -latches " + args[++argidx];
continue;
}
if (args[argidx] == "-noshare") { if (args[argidx] == "-noshare") {
noshare = true; noshare = true;
continue; continue;
@ -276,7 +284,7 @@ struct SynthPass : public ScriptPass {
} }
if (check_label("coarse")) { if (check_label("coarse")) {
run("proc"); run("proc" + latches_opt);
if (flatten || help_mode) { if (flatten || help_mode) {
run("check"); run("check");
run("flatten", " (if -flatten)"); run("flatten", " (if -flatten)");

19
techlibs/efinix/synth_efinix.cc
View file

@ -63,13 +63,19 @@ struct SynthEfinixPass : public ScriptPass
log(" -nobram\n"); log(" -nobram\n");
log(" do not use EFX_RAM_5K cells in output netlist\n"); log(" do not use EFX_RAM_5K cells in output netlist\n");
log("\n"); log("\n");
log(" -latches <info|warn|error>\n");
log(" select the behaviour for latches that cannot be mapped to a\n");
log(" dedicated hardware primitive and are implemented using LUTs\n");
log(" instead. 'error' (the default) aborts synthesis, 'warn' only\n");
log(" prints a warning, and 'info' permits them with an info-level message.\n");
log("\n");
log("\n"); log("\n");
log("The following commands are executed by this synthesis command:\n"); log("The following commands are executed by this synthesis command:\n");
help_script(); help_script();
log("\n"); log("\n");
} }
string top_opt, edif_file, json_file; string top_opt, edif_file, json_file, latches;
bool flatten, retime, nobram; bool flatten, retime, nobram;
void clear_flags() override void clear_flags() override
@ -80,6 +86,7 @@ struct SynthEfinixPass : public ScriptPass
flatten = true; flatten = true;
retime = false; retime = false;
nobram = false; nobram = false;
latches = "error";
} }
void execute(std::vector<std::string> args, RTLIL::Design *design) override void execute(std::vector<std::string> args, RTLIL::Design *design) override
@ -122,12 +129,18 @@ struct SynthEfinixPass : public ScriptPass
nobram = true; nobram = true;
continue; continue;
} }
if (args[argidx] == "-latches" && argidx+1 < args.size()) {
latches = args[++argidx];
continue;
}
break; break;
} }
extra_args(args, argidx, design); extra_args(args, argidx, design);
if (!design->full_selection()) if (!design->full_selection())
log_cmd_error("This command only operates on fully selected designs!\n"); log_cmd_error("This command only operates on fully selected designs!\n");
if (latches != "info" && latches != "warn" && latches != "error")
log_cmd_error("Invalid value '%s' for -latches (expected info, warn or error)\n", latches.c_str());
log_header(design, "Executing SYNTH_EFINIX pass.\n"); log_header(design, "Executing SYNTH_EFINIX pass.\n");
log_push(); log_push();
@ -147,7 +160,7 @@ struct SynthEfinixPass : public ScriptPass
if (flatten && check_label("flatten", "(unless -noflatten)")) if (flatten && check_label("flatten", "(unless -noflatten)"))
{ {
run("proc"); run("proc -latches " + (latches == "info" ? std::string("info") : std::string("warn")));
run("check"); run("check");
run("flatten"); run("flatten");
run("tribuf -logic"); run("tribuf -logic");
@ -190,6 +203,8 @@ struct SynthEfinixPass : public ScriptPass
if (check_label("map_ffs")) if (check_label("map_ffs"))
{ {
run("dfflegalize -cell $_DFFE_????_ 0 -cell $_SDFFE_????_ 0 -cell $_SDFFCE_????_ 0 -cell $_DLATCH_?_ x"); run("dfflegalize -cell $_DFFE_????_ 0 -cell $_SDFFE_????_ 0 -cell $_SDFFCE_????_ 0 -cell $_DLATCH_?_ x");
if (latches == "error" || help_mode)
run("check -latchonly -assert", "(only if -latches error, the default)");
run("techmap -D NO_LUT -map +/efinix/cells_map.v"); run("techmap -D NO_LUT -map +/efinix/cells_map.v");
run("opt_expr -mux_undef"); run("opt_expr -mux_undef");
run("simplemap"); run("simplemap");

19
techlibs/fabulous/synth_fabulous.cc
View file

@ -110,13 +110,19 @@ struct SynthPass : public ScriptPass {
log(" read/write collision\" (same result as setting the no_rw_check\n"); log(" read/write collision\" (same result as setting the no_rw_check\n");
log(" attribute on all memories).\n"); log(" attribute on all memories).\n");
log("\n"); log("\n");
log(" -latches <info|warn|error>\n");
log(" select the behaviour for latches that cannot be mapped to a\n");
log(" dedicated hardware primitive and are implemented using LUTs\n");
log(" instead. 'error' (the default) aborts synthesis, 'warn' only\n");
log(" prints a warning, and 'info' permits them with an info-level message.\n");
log("\n");
log("\n"); log("\n");
log("The following commands are executed by this synthesis command:\n"); log("The following commands are executed by this synthesis command:\n");
help_script(); help_script();
log("\n"); log("\n");
} }
string top_module, json_file, fsm_opts, memory_opts, carry_mode, cells_map, arith_map, clkbuf_map, multiplier_map; string top_module, json_file, fsm_opts, memory_opts, carry_mode, cells_map, arith_map, clkbuf_map, multiplier_map, latches;
std::vector<string> extra_plib, extra_map, extra_mlibmap; std::vector<string> extra_plib, extra_map, extra_mlibmap;
std::vector<std::pair<string, string>> extra_ffs; std::vector<std::pair<string, string>> extra_ffs;
@ -135,6 +141,7 @@ struct SynthPass : public ScriptPass {
carry_mode = "none"; carry_mode = "none";
flatten = true; flatten = true;
json_file = ""; json_file = "";
latches = "error";
} }
void execute(std::vector<std::string> args, RTLIL::Design *design) override void execute(std::vector<std::string> args, RTLIL::Design *design) override
@ -244,12 +251,18 @@ struct SynthPass : public ScriptPass {
flatten = false; flatten = false;
continue; continue;
} }
if (args[argidx] == "-latches" && argidx+1 < args.size()) {
latches = args[++argidx];
continue;
}
break; break;
} }
extra_args(args, argidx, design); extra_args(args, argidx, design);
if (!design->full_selection()) if (!design->full_selection())
log_cmd_error("This command only operates on fully selected designs!\n"); log_cmd_error("This command only operates on fully selected designs!\n");
if (latches != "info" && latches != "warn" && latches != "error")
log_cmd_error("Invalid value '%s' for -latches (expected info, warn or error)\n", latches.c_str());
log_header(design, "Executing SYNTH_FABULOUS pass.\n"); log_header(design, "Executing SYNTH_FABULOUS pass.\n");
log_push(); log_push();
@ -276,7 +289,7 @@ struct SynthPass : public ScriptPass {
run("hierarchy -check"); run("hierarchy -check");
} else } else
run(stringf("hierarchy -check -top %s", top_module)); run(stringf("hierarchy -check -top %s", top_module));
run("proc"); run("proc -latches " + (latches == "info" ? std::string("info") : std::string("warn")));
} }
if (check_label("flatten", "(unless -noflatten)")) { if (check_label("flatten", "(unless -noflatten)")) {
@ -385,6 +398,8 @@ struct SynthPass : public ScriptPass {
dff_str += stringf(" -cell %s %s", cell, init); dff_str += stringf(" -cell %s %s", cell, init);
run(dff_str); run(dff_str);
} }
if (latches == "error" || help_mode)
run("check -latchonly -assert", "(only if -latches error, the default)");
run("opt_merge"); run("opt_merge");
} }

19
techlibs/ice40/synth_ice40.cc
View file

@ -117,13 +117,19 @@ struct SynthIce40Pass : public ScriptPass
log(" read/write collision\" (same result as setting the no_rw_check\n"); log(" read/write collision\" (same result as setting the no_rw_check\n");
log(" attribute on all memories).\n"); log(" attribute on all memories).\n");
log("\n"); log("\n");
log(" -latches <info|warn|error>\n");
log(" select the behaviour for latches that cannot be mapped to a\n");
log(" dedicated hardware primitive and are implemented using LUTs\n");
log(" instead. 'error' (the default) aborts synthesis, 'warn' only\n");
log(" prints a warning, and 'info' permits them with an info-level message.\n");
log("\n");
log("\n"); log("\n");
log("The following commands are executed by this synthesis command:\n"); log("The following commands are executed by this synthesis command:\n");
help_script(); help_script();
log("\n"); log("\n");
} }
string top_opt, blif_file, edif_file, json_file, device_opt; string top_opt, blif_file, edif_file, json_file, device_opt, latches;
bool nocarry, nodffe, nobram, spram, dsp, flatten, retime, noabc, abc2, vpr, abc9, dff, flowmap, no_rw_check; bool nocarry, nodffe, nobram, spram, dsp, flatten, retime, noabc, abc2, vpr, abc9, dff, flowmap, no_rw_check;
int min_ce_use; int min_ce_use;
@ -148,6 +154,7 @@ struct SynthIce40Pass : public ScriptPass
flowmap = false; flowmap = false;
device_opt = "hx"; device_opt = "hx";
no_rw_check = false; no_rw_check = false;
latches = "error";
} }
void execute(std::vector<std::string> args, RTLIL::Design *design) override void execute(std::vector<std::string> args, RTLIL::Design *design) override
@ -258,6 +265,10 @@ struct SynthIce40Pass : public ScriptPass
no_rw_check = true; no_rw_check = true;
continue; continue;
} }
if (args[argidx] == "-latches" && argidx+1 < args.size()) {
latches = args[++argidx];
continue;
}
break; break;
} }
extra_args(args, argidx, design); extra_args(args, argidx, design);
@ -266,6 +277,8 @@ struct SynthIce40Pass : public ScriptPass
log_cmd_error("This command only operates on fully selected designs!\n"); log_cmd_error("This command only operates on fully selected designs!\n");
if (device_opt != "hx" && device_opt != "lp" && device_opt !="u") if (device_opt != "hx" && device_opt != "lp" && device_opt !="u")
log_cmd_error("Invalid or no device specified: '%s'\n", device_opt); log_cmd_error("Invalid or no device specified: '%s'\n", device_opt);
if (latches != "info" && latches != "warn" && latches != "error")
log_cmd_error("Invalid value '%s' for -latches (expected info, warn or error)\n", latches.c_str());
if (abc9 && retime) if (abc9 && retime)
log_cmd_error("-retime option not currently compatible with -abc9!\n"); log_cmd_error("-retime option not currently compatible with -abc9!\n");
@ -303,7 +316,7 @@ struct SynthIce40Pass : public ScriptPass
{ {
run("read_verilog " + define + " -lib -specify +/ice40/cells_sim.v"); run("read_verilog " + define + " -lib -specify +/ice40/cells_sim.v");
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt)); run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt));
run("proc"); run("proc -latches " + (latches == "info" ? std::string("info") : std::string("warn")));
} }
if (check_label("flatten", "(unless -noflatten)")) if (check_label("flatten", "(unless -noflatten)"))
@ -406,6 +419,8 @@ struct SynthIce40Pass : public ScriptPass
run("abc", " (only if -abc2)"); run("abc", " (only if -abc2)");
run("ice40_opt", "(only if -abc2)"); run("ice40_opt", "(only if -abc2)");
} }
if (latches == "error" || help_mode)
run("check -latchonly -assert", "(only if -latches error, the default)");
run("techmap -map +/ice40/latches_map.v"); run("techmap -map +/ice40/latches_map.v");
if (noabc || flowmap || help_mode) { if (noabc || flowmap || help_mode) {
run("simplemap", " (if -noabc or -flowmap)"); run("simplemap", " (if -noabc or -flowmap)");

24
techlibs/lattice/synth_lattice.cc
View file

@ -156,13 +156,20 @@ struct SynthLatticePass : public ScriptPass
log(" implement constant comparisons in soft logic, do not involve\n"); log(" implement constant comparisons in soft logic, do not involve\n");
log(" hard carry chains\n"); log(" hard carry chains\n");
log("\n"); log("\n");
log(" -latches <info|warn|error>\n");
log(" select the behaviour for latches that cannot be mapped to a\n");
log(" dedicated hardware primitive and are implemented using LUTs\n");
log(" instead. 'error' (the default) aborts synthesis, 'warn' only\n");
log(" prints a warning, and 'info' permits them with an info-level message.\n");
log(" (ignored with -asyncprld, which has a latch primitive)\n");
log("\n");
log("\n"); log("\n");
log("The following commands are executed by this synthesis command:\n"); log("The following commands are executed by this synthesis command:\n");
help_script(); help_script();
log("\n"); log("\n");
} }
string top_opt, edif_file, json_file, family; string top_opt, edif_file, json_file, family, latches;
bool noccu2, nodffe, nobram, nolutram, nowidelut, asyncprld, flatten, dff, retime, abc2, abc9, iopad, nodsp, no_rw_check, have_dsp; bool noccu2, nodffe, nobram, nolutram, nowidelut, asyncprld, flatten, dff, retime, abc2, abc9, iopad, nodsp, no_rw_check, have_dsp;
bool cmp2softlogic; bool cmp2softlogic;
string postfix, arith_map, brams_map, dsp_map, cells_map, map_ram_default, widelut_abc; string postfix, arith_map, brams_map, dsp_map, cells_map, map_ram_default, widelut_abc;
@ -189,6 +196,7 @@ struct SynthLatticePass : public ScriptPass
iopad = false; iopad = false;
nodsp = false; nodsp = false;
no_rw_check = false; no_rw_check = false;
latches = "error";
postfix = ""; postfix = "";
arith_map = ""; arith_map = "";
brams_map = ""; brams_map = "";
@ -318,6 +326,10 @@ struct SynthLatticePass : public ScriptPass
cmp2softlogic = true; cmp2softlogic = true;
continue; continue;
} }
if (args[argidx] == "-latches" && argidx+1 < args.size()) {
latches = args[++argidx];
continue;
}
break; break;
} }
extra_args(args, argidx, design); extra_args(args, argidx, design);
@ -325,6 +337,9 @@ struct SynthLatticePass : public ScriptPass
if (family.empty()) if (family.empty())
log_cmd_error("Lattice family parameter must be set.\n"); log_cmd_error("Lattice family parameter must be set.\n");
if (latches != "info" && latches != "warn" && latches != "error")
log_cmd_error("Invalid value '%s' for -latches (expected info, warn or error)\n", latches.c_str());
if (family == "ecp5") { if (family == "ecp5") {
postfix = "_ecp5"; postfix = "_ecp5";
arith_map = "_ccu2c"; arith_map = "_ccu2c";
@ -401,7 +416,7 @@ struct SynthLatticePass : public ScriptPass
if (check_label("coarse")) if (check_label("coarse"))
{ {
run("proc"); run("proc -latches " + ((asyncprld || latches == "info") ? std::string("info") : std::string("warn")));
if (flatten || help_mode) { if (flatten || help_mode) {
run("check"); run("check");
run("flatten"); run("flatten");
@ -531,8 +546,11 @@ struct SynthLatticePass : public ScriptPass
{ {
if (abc2 || help_mode) if (abc2 || help_mode)
run("abc", " (only if -abc2)"); run("abc", " (only if -abc2)");
if (!asyncprld || help_mode) if (!asyncprld || help_mode) {
if (latches == "error" || help_mode)
run("check -latchonly -assert", "(skip if -asyncprld; only if -latches error, the default)");
run("techmap -map +/lattice/latches_map.v", "(skip if -asyncprld)"); run("techmap -map +/lattice/latches_map.v", "(skip if -asyncprld)");
}
if (abc9) { if (abc9) {
std::string abc9_opts; std::string abc9_opts;

20
techlibs/nanoxplore/synth_nanoxplore.cc
View file

@ -97,13 +97,19 @@ struct SynthNanoXplorePass : public ScriptPass
log(" read/write collision\" (same result as setting the no_rw_check\n"); log(" read/write collision\" (same result as setting the no_rw_check\n");
log(" attribute on all memories).\n"); log(" attribute on all memories).\n");
log("\n"); log("\n");
log(" -latches <info|warn|error>\n");
log(" select the behaviour for latches that cannot be mapped to a\n");
log(" dedicated hardware primitive and are implemented using LUTs\n");
log(" instead. 'error' (the default) aborts synthesis, 'warn' only\n");
log(" prints a warning, and 'info' permits them with an info-level message.\n");
log("\n");
log("\n"); log("\n");
log("The following commands are executed by this synthesis command:\n"); log("The following commands are executed by this synthesis command:\n");
help_script(); help_script();
log("\n"); log("\n");
} }
string top_opt, json_file, family; string top_opt, json_file, family, latches;
bool flatten, abc9, nocy, nodffe, norfram, nobram, noiopad, no_rw_check; bool flatten, abc9, nocy, nodffe, norfram, nobram, noiopad, no_rw_check;
std::string postfix; std::string postfix;
int min_ce_use, min_srst_use; int min_ce_use, min_srst_use;
@ -124,6 +130,7 @@ struct SynthNanoXplorePass : public ScriptPass
postfix = ""; postfix = "";
min_ce_use = 8; min_ce_use = 8;
min_srst_use = 8; min_srst_use = 8;
latches = "error";
} }
void execute(std::vector<std::string> args, RTLIL::Design *design) override void execute(std::vector<std::string> args, RTLIL::Design *design) override
@ -202,10 +209,17 @@ struct SynthNanoXplorePass : public ScriptPass
no_rw_check = true; no_rw_check = true;
continue; continue;
} }
if (args[argidx] == "-latches" && argidx+1 < args.size()) {
latches = args[++argidx];
continue;
}
break; break;
} }
extra_args(args, argidx, design); extra_args(args, argidx, design);
if (latches != "info" && latches != "warn" && latches != "error")
log_cmd_error("Invalid value '%s' for -latches (expected info, warn or error)\n", latches.c_str());
if (family.empty()) { if (family.empty()) {
//log_warning("NanoXplore family not set, setting it to NG-ULTRA.\n"); //log_warning("NanoXplore family not set, setting it to NG-ULTRA.\n");
family = "ultra"; family = "ultra";
@ -249,7 +263,7 @@ struct SynthNanoXplorePass : public ScriptPass
if (check_label("coarse")) if (check_label("coarse"))
{ {
run("proc"); run("proc -latches " + (latches == "info" ? std::string("info") : std::string("warn")));
if (flatten || help_mode) { if (flatten || help_mode) {
run("check"); run("check");
run("flatten", "(skip if -noflatten)"); run("flatten", "(skip if -noflatten)");
@ -325,6 +339,8 @@ struct SynthNanoXplorePass : public ScriptPass
dfflegalize_args += stringf(" -cell $_DLATCH_?_ x -mince %d -minsrst %d", min_ce_use, min_srst_use); dfflegalize_args += stringf(" -cell $_DLATCH_?_ x -mince %d -minsrst %d", min_ce_use, min_srst_use);
run("dfflegalize" + dfflegalize_args,"($_*DFFE_* only if not -nodffe)"); run("dfflegalize" + dfflegalize_args,"($_*DFFE_* only if not -nodffe)");
run("opt_merge"); run("opt_merge");
if (latches == "error" || help_mode)
run("check -latchonly -assert", "(only if -latches error, the default)");
run("techmap -map +/nanoxplore/latches_map.v"); run("techmap -map +/nanoxplore/latches_map.v");
run("techmap -map +/nanoxplore/cells_map.v"); run("techmap -map +/nanoxplore/cells_map.v");
run("opt_expr -undriven -mux_undef"); run("opt_expr -undriven -mux_undef");

21
techlibs/quicklogic/synth_quicklogic.cc
View file

@ -72,12 +72,19 @@ struct SynthQuickLogicPass : public ScriptPass {
log(" use old ABC flow, which has generally worse mapping results but is less\n"); log(" use old ABC flow, which has generally worse mapping results but is less\n");
log(" likely to have bugs.\n"); log(" likely to have bugs.\n");
log("\n"); log("\n");
log(" -latches <info|warn|error>\n");
log(" select the behaviour for latches that cannot be mapped to a\n");
log(" dedicated hardware primitive and are implemented using LUTs\n");
log(" instead. 'error' (the default) aborts synthesis, 'warn' only\n");
log(" prints a warning, and 'info' permits them with an info-level message.\n");
log(" (only applies to the pp3 family)\n");
log("\n");
log("The following commands are executed by this synthesis command:\n"); log("The following commands are executed by this synthesis command:\n");
help_script(); help_script();
log("\n"); log("\n");
} }
string top_opt, blif_file, edif_file, family, currmodule, verilog_file, lib_path; string top_opt, blif_file, edif_file, family, currmodule, verilog_file, lib_path, latches;
bool abc9, inferAdder, nobram, bramTypes, dsp, ioff, flatten; bool abc9, inferAdder, nobram, bramTypes, dsp, ioff, flatten;
void clear_flags() override void clear_flags() override
@ -96,6 +103,7 @@ struct SynthQuickLogicPass : public ScriptPass {
dsp = true; dsp = true;
ioff = true; ioff = true;
flatten = true; flatten = true;
latches = "error";
} }
void set_scratchpad_defaults(RTLIL::Design *design) { void set_scratchpad_defaults(RTLIL::Design *design) {
@ -168,6 +176,10 @@ struct SynthQuickLogicPass : public ScriptPass {
flatten = false; flatten = false;
continue; continue;
} }
if (args[argidx] == "-latches" && argidx+1 < args.size()) {
latches = args[++argidx];
continue;
}
break; break;
} }
extra_args(args, argidx, design); extra_args(args, argidx, design);
@ -178,6 +190,9 @@ struct SynthQuickLogicPass : public ScriptPass {
if (family != "pp3" && family != "qlf_k6n10f") if (family != "pp3" && family != "qlf_k6n10f")
log_cmd_error("Invalid family specified: '%s'\n", family); log_cmd_error("Invalid family specified: '%s'\n", family);
if (latches != "info" && latches != "warn" && latches != "error")
log_cmd_error("Invalid value '%s' for -latches (expected info, warn or error)\n", latches.c_str());
if (abc9 && design->scratchpad_get_int("abc9.D", 0) == 0) { if (abc9 && design->scratchpad_get_int("abc9.D", 0) == 0) {
log_warning("delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.\n"); log_warning("delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.\n");
design->scratchpad_set_int("abc9.D", 41667); // 12MHz = 83.33.. ns; divided by two to allow for interconnect delay. design->scratchpad_set_int("abc9.D", 41667); // 12MHz = 83.33.. ns; divided by two to allow for interconnect delay.
@ -211,7 +226,7 @@ struct SynthQuickLogicPass : public ScriptPass {
} }
if (check_label("prepare")) { if (check_label("prepare")) {
run("proc"); run("proc -latches " + ((family == "pp3" && latches != "info") ? std::string("warn") : std::string("info")));
if (flatten) { if (flatten) {
run("check"); run("check");
run("flatten", "(unless -noflatten)"); run("flatten", "(unless -noflatten)");
@ -315,6 +330,8 @@ struct SynthQuickLogicPass : public ScriptPass {
} }
if (check_label("map_luts", "(for pp3)") && (help_mode || family == "pp3")) { if (check_label("map_luts", "(for pp3)") && (help_mode || family == "pp3")) {
if (latches == "error" || help_mode)
run("check -latchonly -assert", "(only if -latches error, the default)");
run("techmap -map " + lib_path + family + "/latches_map.v"); run("techmap -map " + lib_path + family + "/latches_map.v");
if (abc9) { if (abc9) {
run("read_verilog -lib -specify -icells " + lib_path + family + "/abc9_model.v"); run("read_verilog -lib -specify -icells " + lib_path + family + "/abc9_model.v");

6
tests/arch/ecp5/latches.ys
View file

@ -4,7 +4,7 @@ design -save read
hierarchy -top latchp hierarchy -top latchp
proc proc
# Can't run any sort of equivalence check because latches are blown to LUTs # Can't run any sort of equivalence check because latches are blown to LUTs
synth_ecp5 synth_ecp5 -latches info
cd latchp # Constrain all select calls below inside the top module cd latchp # Constrain all select calls below inside the top module
select -assert-count 1 t:LUT4 select -assert-count 1 t:LUT4
@ -15,7 +15,7 @@ design -load read
hierarchy -top latchn hierarchy -top latchn
proc proc
# Can't run any sort of equivalence check because latches are blown to LUTs # Can't run any sort of equivalence check because latches are blown to LUTs
synth_ecp5 synth_ecp5 -latches info
cd latchn # Constrain all select calls below inside the top module cd latchn # Constrain all select calls below inside the top module
select -assert-count 1 t:LUT4 select -assert-count 1 t:LUT4
@ -26,7 +26,7 @@ design -load read
hierarchy -top latchsr hierarchy -top latchsr
proc proc
# Can't run any sort of equivalence check because latches are blown to LUTs # Can't run any sort of equivalence check because latches are blown to LUTs
synth_ecp5 synth_ecp5 -latches info
cd latchsr # Constrain all select calls below inside the top module cd latchsr # Constrain all select calls below inside the top module
select -assert-count 2 t:LUT4 select -assert-count 2 t:LUT4
select -assert-count 1 t:PFUMX select -assert-count 1 t:PFUMX

2
tests/arch/ecp5/latches_abc9.ys
View file

@ -8,6 +8,6 @@ assign q = ~l;
endmodule endmodule
EOT EOT
# Can't run any sort of equivalence check because latches are blown to LUTs # Can't run any sort of equivalence check because latches are blown to LUTs
synth_ecp5 -abc9 synth_ecp5 -abc9 -latches info
select -assert-count 2 t:LUT4 select -assert-count 2 t:LUT4
select -assert-none t:LUT4 %% t:* %D select -assert-none t:LUT4 %% t:* %D

6
tests/arch/efinix/latches.ys
View file

@ -4,7 +4,7 @@ design -save read
hierarchy -top latchp hierarchy -top latchp
proc proc
# Can't run any sort of equivalence check because latches are blown to LUTs # Can't run any sort of equivalence check because latches are blown to LUTs
synth_efinix synth_efinix -latches info
cd latchp # Constrain all select calls below inside the top module cd latchp # Constrain all select calls below inside the top module
select -assert-count 1 t:EFX_LUT4 select -assert-count 1 t:EFX_LUT4
@ -15,7 +15,7 @@ design -load read
hierarchy -top latchn hierarchy -top latchn
proc proc
# Can't run any sort of equivalence check because latches are blown to LUTs # Can't run any sort of equivalence check because latches are blown to LUTs
synth_efinix synth_efinix -latches info
cd latchn # Constrain all select calls below inside the top module cd latchn # Constrain all select calls below inside the top module
select -assert-count 1 t:EFX_LUT4 select -assert-count 1 t:EFX_LUT4
@ -26,7 +26,7 @@ design -load read
hierarchy -top latchsr hierarchy -top latchsr
proc proc
# Can't run any sort of equivalence check because latches are blown to LUTs # Can't run any sort of equivalence check because latches are blown to LUTs
synth_efinix synth_efinix -latches info
cd latchsr # Constrain all select calls below inside the top module cd latchsr # Constrain all select calls below inside the top module
select -assert-count 2 t:EFX_LUT4 select -assert-count 2 t:EFX_LUT4

6
tests/arch/ice40/latches.ys
View file

@ -4,7 +4,7 @@ design -save read
hierarchy -top latchp hierarchy -top latchp
proc proc
# Can't run any sort of equivalence check because latches are blown to LUTs # Can't run any sort of equivalence check because latches are blown to LUTs
synth_ice40 synth_ice40 -latches info
cd latchp # Constrain all select calls below inside the top module cd latchp # Constrain all select calls below inside the top module
select -assert-count 1 t:SB_LUT4 select -assert-count 1 t:SB_LUT4
@ -15,7 +15,7 @@ design -load read
hierarchy -top latchn hierarchy -top latchn
proc proc
# Can't run any sort of equivalence check because latches are blown to LUTs # Can't run any sort of equivalence check because latches are blown to LUTs
synth_ice40 synth_ice40 -latches info
cd latchn # Constrain all select calls below inside the top module cd latchn # Constrain all select calls below inside the top module
select -assert-count 1 t:SB_LUT4 select -assert-count 1 t:SB_LUT4
@ -26,7 +26,7 @@ design -load read
hierarchy -top latchsr hierarchy -top latchsr
proc proc
# Can't run any sort of equivalence check because latches are blown to LUTs # Can't run any sort of equivalence check because latches are blown to LUTs
synth_ice40 synth_ice40 -latches info
cd latchsr # Constrain all select calls below inside the top module cd latchsr # Constrain all select calls below inside the top module
select -assert-count 2 t:SB_LUT4 select -assert-count 2 t:SB_LUT4

6
tests/arch/nanoxplore/latches.ys
View file

@ -4,7 +4,7 @@ design -save read
hierarchy -top latchp hierarchy -top latchp
proc proc
# Can't run any sort of equivalence check because latches are blown to LUTs # Can't run any sort of equivalence check because latches are blown to LUTs
synth_nanoxplore -noiopad synth_nanoxplore -noiopad -latches info
cd latchp # Constrain all select calls below inside the top module cd latchp # Constrain all select calls below inside the top module
select -assert-count 1 t:NX_LUT select -assert-count 1 t:NX_LUT
@ -15,7 +15,7 @@ design -load read
hierarchy -top latchn hierarchy -top latchn
proc proc
# Can't run any sort of equivalence check because latches are blown to LUTs # Can't run any sort of equivalence check because latches are blown to LUTs
synth_nanoxplore -noiopad synth_nanoxplore -noiopad -latches info
cd latchn # Constrain all select calls below inside the top module cd latchn # Constrain all select calls below inside the top module
select -assert-count 1 t:NX_LUT select -assert-count 1 t:NX_LUT
@ -26,7 +26,7 @@ design -load read
hierarchy -top latchsr hierarchy -top latchsr
proc proc
# Can't run any sort of equivalence check because latches are blown to LUTs # Can't run any sort of equivalence check because latches are blown to LUTs
synth_nanoxplore -noiopad synth_nanoxplore -noiopad -latches info
cd latchsr # Constrain all select calls below inside the top module cd latchsr # Constrain all select calls below inside the top module
select -assert-count 2 t:NX_LUT select -assert-count 2 t:NX_LUT

6
tests/arch/quicklogic/pp3/latches.ys
View file

@ -4,7 +4,7 @@ design -save read
hierarchy -top latchp hierarchy -top latchp
proc proc
# Can't run any sort of equivalence check because latches are blown to LUTs # Can't run any sort of equivalence check because latches are blown to LUTs
synth_quicklogic synth_quicklogic -latches info
cd latchp # Constrain all select calls below inside the top module cd latchp # Constrain all select calls below inside the top module
select -assert-count 1 t:LUT3 select -assert-count 1 t:LUT3
select -assert-count 3 t:inpad select -assert-count 3 t:inpad
@ -17,7 +17,7 @@ design -load read
hierarchy -top latchn hierarchy -top latchn
proc proc
# Can't run any sort of equivalence check because latches are blown to LUTs # Can't run any sort of equivalence check because latches are blown to LUTs
synth_quicklogic synth_quicklogic -latches info
cd latchn # Constrain all select calls below inside the top module cd latchn # Constrain all select calls below inside the top module
select -assert-count 1 t:LUT3 select -assert-count 1 t:LUT3
select -assert-count 3 t:inpad select -assert-count 3 t:inpad
@ -30,7 +30,7 @@ design -load read
hierarchy -top latchsr hierarchy -top latchsr
proc proc
# Can't run any sort of equivalence check because latches are blown to LUTs # Can't run any sort of equivalence check because latches are blown to LUTs
synth_quicklogic synth_quicklogic -latches info
cd latchsr # Constrain all select calls below inside the top module cd latchsr # Constrain all select calls below inside the top module
select -assert-count 1 t:LUT2 select -assert-count 1 t:LUT2
select -assert-count 1 t:LUT4 select -assert-count 1 t:LUT4

32
tests/proc/proc_latches.ys Normal file
View file

@ -0,0 +1,32 @@
# warn
read_verilog <<EOT
module top(input g, rn, d, output reg q);
always @* if (~rn) q <= 0; else if (g) q <= d;
endmodule
EOT
logger -expect warning "Latch inferred for signal" 1
proc
logger -check-expected
design -reset
# info
read_verilog <<EOT
module top(input g, rn, d, output reg q);
always @* if (~rn) q <= 0; else if (g) q <= d;
endmodule
EOT
logger -expect-no-warnings
proc -latches info
logger -check-expected
design -reset
# error
read_verilog <<EOT
module top(input g, rn, d, output reg q);
always @* if (~rn) q <= 0; else if (g) q <= d;
endmodule
EOT
logger -expect error "Latch inferred for signal" 1
proc -latches error

35
tests/various/check_nolatches.ys Normal file
View file

@ -0,0 +1,35 @@
design -reset
read_verilog <<EOT
module top(input g, d, output reg q);
always @* if (g) q = d;
endmodule
EOT
hierarchy -top top
proc
select -assert-count 1 t:$dlatch
logger -expect warning "is a latch of type" 1
check -nolatches
logger -check-expected
design -reset
read_verilog <<EOT
module top(input g, d, output reg q);
always @* q = g ? d : 1'b0;
endmodule
EOT
hierarchy -top top
proc
check -nolatches -assert
design -reset
read_verilog <<EOT
module top(input g, d, output reg q, output y);
always @* if (g) q = d;
wire u;
assign y = u;
endmodule
EOT
hierarchy -top top
proc
logger -expect error "Found [0-9]+ problems in 'check -assert'" 1
check -latchonly -assert

20
tests/various/synth_latch_warning.ys Normal file
View file

@ -0,0 +1,20 @@
read_verilog <<EOT
module top(input d, en, output reg q);
always @* if (en) q = d;
endmodule
EOT
design -save read
logger -expect warning "Latch inferred for signal" 1
synth_ice40 -latches warn
logger -check-expected
select -assert-count 1 t:SB_LUT4
design -load read
synth_ice40 -latches info
select -assert-count 1 t:SB_LUT4
design -load read
logger -expect warning "Latch inferred for signal" 1
logger -expect error "Found 1 problems in 'check -assert'" 1
synth_ice40