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Merge pull request #1623 from YosysHQ/mmicko/edif_attr
Export wire properties in EDIF
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commit
9fbeb57bbd
5 changed files with 46 additions and 35 deletions
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@ -4,8 +4,8 @@ proc
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equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 14 t:LUT2
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select -assert-count 6 t:MUXCY
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select -assert-count 8 t:XORCY
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select -assert-none t:LUT2 t:MUXCY t:XORCY %% t:* %D
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stat
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select -assert-count 16 t:LUT2
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select -assert-count 2 t:CARRY4
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select -assert-none t:LUT2 t:CARRY4 %% t:* %D
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@ -5,10 +5,9 @@ flatten
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equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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stat
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select -assert-count 1 t:BUFG
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select -assert-count 8 t:FDCE
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select -assert-count 1 t:INV
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select -assert-count 7 t:MUXCY
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select -assert-count 8 t:XORCY
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select -assert-none t:BUFG t:FDCE t:INV t:MUXCY t:XORCY %% t:* %D
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select -assert-count 2 t:CARRY4
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select -assert-none t:BUFG t:FDCE t:INV t:CARRY4 %% t:* %D
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@ -9,7 +9,7 @@ sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd fsm # Constrain all select calls below inside the top module
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stat
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select -assert-count 1 t:BUFG
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select -assert-count 4 t:FDRE
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select -assert-count 1 t:FDSE
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