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Merge pull request #1623 from YosysHQ/mmicko/edif_attr

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Export wire properties in EDIF
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Miodrag Milanović 2020-01-14 19:19:32 +01:00 • committed by GitHub
commit 9fbeb57bbd
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5 changed files with 46 additions and 35 deletions
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techlibs/xilinx/synth_xilinx.cc
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@ -518,7 +518,7 @@ struct SynthXilinxPass : public ScriptPass
techmap_args += " -map +/xilinx/arith_map.v";
if (vpr)
techmap_args += " -D _EXPLICIT_CARRY";
else if (abc9)
else
techmap_args += " -D _CLB_CARRY";
}
run("techmap " + techmap_args);