mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-05 19:00:26 +00:00
Code Activity

Transform "$.*" to ID("$.*") in passes/techmap

Browse source
This commit is contained in:
Eddie Hung 2019-08-15 10:05:08 -07:00
parent 4cfefae21e
commit 9f98241010
24 changed files with 356 additions and 361 deletions
Download patch file Download diff file Expand all files Collapse all files

12
passes/techmap/extract_fa.cc
View file

@ -85,9 +85,9 @@ struct ExtractFaWorker
{
for (auto cell : module->selected_cells())
{
if (cell->type.in( "$_BUF_", "$_NOT_", "$_AND_", "$_NAND_", "$_OR_", "$_NOR_",
"$_XOR_", "$_XNOR_", "$_ANDNOT_", "$_ORNOT_", "$_MUX_", "$_NMUX_",
"$_AOI3_", "$_OAI3_", "$_AOI4_", "$_OAI4_"))
if (cell->type.in( ID($_BUF_), ID($_NOT_), ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_),
ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_), ID($_MUX_), ID($_NMUX_),
ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_)))
{
SigBit y = sigmap(SigBit(cell->getPort("\\Y")));
log_assert(driver.count(y) == 0);
@ -289,7 +289,7 @@ struct ExtractFaWorker
for (auto it : driver)
{
if (it.second->type.in("$_BUF_", "$_NOT_"))
if (it.second->type.in(ID($_BUF_), ID($_NOT_)))
continue;
SigBit root = it.first;
@ -390,7 +390,7 @@ struct ExtractFaWorker
}
else
{
Cell *cell = module->addCell(NEW_ID, "$fa");
Cell *cell = module->addCell(NEW_ID, ID($fa));
cell->setParam("\\WIDTH", 1);
log(" Created $fa cell %s.\n", log_id(cell));
@ -496,7 +496,7 @@ struct ExtractFaWorker
}
else
{
Cell *cell = module->addCell(NEW_ID, "$fa");
Cell *cell = module->addCell(NEW_ID, ID($fa));
cell->setParam("\\WIDTH", 1);
log(" Created $fa cell %s.\n", log_id(cell));