From b16cdaab35050ca51a696b6c8e191ffb19946d0f Mon Sep 17 00:00:00 2001 From: Richard Herveille Date: Wed, 6 Mar 2024 02:43:30 +0100 Subject: [PATCH 1/7] dsp_map for MAX10 --- techlibs/intel/max10/dsp_map.v | 73 ++++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) create mode 100644 techlibs/intel/max10/dsp_map.v diff --git a/techlibs/intel/max10/dsp_map.v b/techlibs/intel/max10/dsp_map.v new file mode 100644 index 000000000..1c7827b5e --- /dev/null +++ b/techlibs/intel/max10/dsp_map.v @@ -0,0 +1,73 @@ +module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 0; + parameter B_WIDTH = 0; + parameter Y_WIDTH = 0; + + wire [A_WIDTH+B_WIDTH-1:0] mult_result; + + fiftyfivenm_mac_mult #( + .dataa_clock ("none"), + .datab_clock ("none"), + .signa_clock ("none"), + .signb_clock ("none"), + .dataa_width (A_WIDTH), + .datab_width (B_WIDTH), + .lpm_type ("fiftyfivenm_mac_mult") + ) _TECHMAP_REPLACE_mac_mult ( + //Data path + .dataa ( A ), + .datab ( B ), + .dataout( mult_result ), + .signa ( A_SIGNED != 0 ? 1'b1 : 1'b0), + .signb ( B_SIGNED != 0 ? 1'b1 : 1'b0) + ); + + fiftyfivenm_mac_out #( + .dataa_width (A_WIDTH + B_WIDTH), + .output_clock ("none"), + .lpm_type ("fiftyfivenm_mac_out") + ) _TECHMAP_REPLACE_mac_out ( + .dataa (mult_result), + .dataout (Y) + ); +endmodule + + +module \$__MUL9X9 (input [8:0] A, input [8:0] B, output [17:0] Y); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 0; + parameter B_WIDTH = 0; + parameter Y_WIDTH = 0; + + wire [A_WIDTH+B_WIDTH-1:0] mult_result; + + fiftyfivenm_mac_mult #( + .dataa_clock ("none"), + .datab_clock ("none"), + .signa_clock ("none"), + .signb_clock ("none"), + .dataa_width (A_WIDTH), + .datab_width (B_WIDTH), + .lpm_type ("fiftyfivenm_mac_mult") + ) _TECHMAP_REPLACE_mac_mult ( + //Data path + .dataa ( A ), + .datab ( B ), + .dataout( mult_result ), + .signa ( A_SIGNED != 0 ? 1'b1 : 1'b0), + .signb ( B_SIGNED != 0 ? 1'b1 : 1'b0) + ); + + fiftyfivenm_mac_out #( + .dataa_width (A_WIDTH + B_WIDTH), + .output_clock ("none"), + .lpm_type ("fiftyfivenm_mac_out") + ) _TECHMAP_REPLACE_mac_out ( + .dataa (mult_result), + .dataout (Y) + ); +endmodule + From 2fde482629dd523f196b231c6659609ff768a20f Mon Sep 17 00:00:00 2001 From: Richard Herveille Date: Wed, 6 Mar 2024 02:45:07 +0100 Subject: [PATCH 2/7] Fixed data/address width parameters --- techlibs/intel/common/brams_map_m9k.v | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/techlibs/intel/common/brams_map_m9k.v b/techlibs/intel/common/brams_map_m9k.v index d0f07c1de..c80ebe3f4 100644 --- a/techlibs/intel/common/brams_map_m9k.v +++ b/techlibs/intel/common/brams_map_m9k.v @@ -63,10 +63,10 @@ module \$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1A .width_byteena_a (1), // Forced value .numwords_b ( NUMWORDS ), .numwords_a ( NUMWORDS ), - .widthad_b ( CFG_DBITS ), - .width_b ( CFG_ABITS ), - .widthad_a ( CFG_DBITS ), - .width_a ( CFG_ABITS ) + .widthad_b ( CFG_ABITS ), + .width_b ( CFG_DBITS ), + .widthad_a ( CFG_ABITS ), + .width_a ( CFG_DBITS ) ) _TECHMAP_REPLACE_ ( .data_a(B1DATA), .address_a(B1ADDR), From 58b1522a20ef9a4ec914280bcaf4f4e637f4368e Mon Sep 17 00:00:00 2001 From: Richard Herveille Date: Wed, 6 Mar 2024 02:45:29 +0100 Subject: [PATCH 3/7] Added DSP macros --- techlibs/intel/max10/cells_sim.v | 56 +++++++++++++++++++++++++++++++- 1 file changed, 55 insertions(+), 1 deletion(-) diff --git a/techlibs/intel/max10/cells_sim.v b/techlibs/intel/max10/cells_sim.v index 7705fa27a..d273b47d6 100644 --- a/techlibs/intel/max10/cells_sim.v +++ b/techlibs/intel/max10/cells_sim.v @@ -2,6 +2,7 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Claire Xenia Wolf + * Copyright (C) 2024 Richard Herveille * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -289,4 +290,57 @@ module fiftyfivenm_pll output vcooverrange; output vcounderrange; -endmodule // cycloneive_pll +endmodule // max10_pll + + +//rih +/* MAX10 MULT clearbox model */ +(* blackbox *) +module fiftyfivenm_mac_mult ( + dataa, + datab, + dataout, + signa, + signb, + + aclr, + clk, + ena +); + parameter dataa_clock = "none"; + parameter dataa_width = 18; + parameter datab_clock = "none"; + parameter datab_width = 18; + parameter signa_clock = "none"; + parameter signb_clock = "none"; + parameter lpm_type = "fiftyfivenm_mac_mult"; + + input [dataa_width -1:0] dataa; + input [datab_width -1:0] datab; + output [(dataa_width+datab_width)-1:0] dataout; + input signa; + input signb; + input aclr; + input clk; + input ena; +endmodule : fiftyfivenm_mac_mult + +module fiftyfivenm_mac_out ( + dataa, + dataout, + + aclr, + clk, + ena +); + + parameter dataa_width = 38; + parameter output_clock = "none"; + parameter lpm_type = "fiftyfivenm_mac_out"; + + input [dataa_width-1:0] dataa; + output [dataa_width-1:0] dataout; + input aclr; + input clk; + input ena; +endmodule : fiftyfivenm_mac_out From 1723aa251afa492898b4046ff4dc867a1265d6c5 Mon Sep 17 00:00:00 2001 From: Richard Herveille Date: Wed, 6 Mar 2024 02:45:40 +0100 Subject: [PATCH 4/7] Added DSP support and updates for performance --- techlibs/intel/synth_intel.cc | 65 ++++++++++++++++++++++++++++++++--- 1 file changed, 61 insertions(+), 4 deletions(-) diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index e9594e6d8..00e5766e9 100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -2,6 +2,7 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Claire Xenia Wolf + * Copyright (C) 2024 Richard Herveille * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -62,12 +63,19 @@ struct SynthIntelPass : public ScriptPass { log(" from label is synonymous to 'begin', and empty to label is\n"); log(" synonymous to the end of the command list.\n"); log("\n"); + log(" -dff\n"); + log(" pass DFFs to ABC to perform sequential logic optimisations\n"); + log(" (EXPERIMENTAL)\n"); + log("\n"); log(" -iopads\n"); log(" use IO pad cells in output netlist\n"); log("\n"); log(" -nobram\n"); log(" do not use block RAM cells in output netlist\n"); log("\n"); + log(" -nodsp\n"); + log(" do not map multipliers to MUL18/MUL9 cells\n"); + log("\n"); log(" -noflatten\n"); log(" do not flatten design before synthesis\n"); log("\n"); @@ -80,7 +88,7 @@ struct SynthIntelPass : public ScriptPass { } string top_opt, family_opt, vout_file, blif_file; - bool retime, flatten, nobram, iopads; + bool retime, flatten, nobram, dff, nodsp, iopads; void clear_flags() override { @@ -91,6 +99,8 @@ struct SynthIntelPass : public ScriptPass { retime = false; flatten = true; nobram = false; + dff = false; + nodsp = false; iopads = false; } @@ -130,6 +140,14 @@ struct SynthIntelPass : public ScriptPass { iopads = true; continue; } + if (args[argidx] == "-dff") { + dff = true; + continue; + } + if (args[argidx] == "-nodsp") { + nodsp = true; + continue; + } if (args[argidx] == "-nobram") { nobram = true; continue; @@ -177,16 +195,52 @@ struct SynthIntelPass : public ScriptPass { run("read_verilog -sv -lib +/intel/common/altpll_bb.v"); run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt.c_str())); } - +/* if (flatten && check_label("flatten", "(unless -noflatten)")) { run("proc"); run("flatten"); run("tribuf -logic"); run("deminout"); } +*/ if (check_label("coarse")) { - run("synth -run coarse"); +// run("synth -run coarse"); + run("proc"); + if (flatten || help_mode) + run("flatten", "(skip if -noflatten)"); + run("tribuf -logic"); + run("deminout"); + run("opt_expr"); + run("opt_clean"); + run("check"); + run("opt -nodffe -nosdff"); + run("fsm"); + run("opt"); + run("wreduce"); + run("peepopt"); + run("opt_clean"); + run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4"); + run("opt_expr"); + run("opt_clean"); + + if (help_mode) { + run("techmap -map +mul2dsp.v [...]", "(unless -nodsp)"); + } else if (!nodsp) { + run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=10 -D DSP_B_MINWIDTH=4 -D DSP_NAME=$__MUL18X18"); + run("chtype -set $mul t:$__soft_mul"); + run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=10 -D DSP_NAME=$__MUL18X18"); + run("chtype -set $mul t:$__soft_mul"); + run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=9 -D DSP_B_MAXWIDTH=9 -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=4 -D DSP_NAME=$__MUL9X9"); + run("chtype -set $mul t:$__soft_mul"); + run("alumacc"); + run(stringf("techmap -map +/intel/%s/dsp_map.v", family_opt.c_str())); + } else { + run("alumacc"); + } + run("opt"); + run("memory -nomap"); + run("opt_clean"); } if (!nobram && check_label("map_bram", "(skip if -nobram)")) { @@ -219,7 +273,10 @@ struct SynthIntelPass : public ScriptPass { } if (check_label("map_luts")) { - run("abc -lut 4" + string(retime ? " -dff" : "")); + run("abc9 -lut 4 -W 300" + string(dff ? " -dff" : "")); + run("clean"); + run("opt -fast"); + run("autoname"); run("clean"); } From 2d11c5e2f8199065039b7ac07e60622f9c2c583d Mon Sep 17 00:00:00 2001 From: Richard Herveille Date: Fri, 15 Mar 2024 01:48:06 +0100 Subject: [PATCH 5/7] removed comment --- techlibs/intel/max10/cells_sim.v | 1 - 1 file changed, 1 deletion(-) diff --git a/techlibs/intel/max10/cells_sim.v b/techlibs/intel/max10/cells_sim.v index d273b47d6..fe8c92b0a 100644 --- a/techlibs/intel/max10/cells_sim.v +++ b/techlibs/intel/max10/cells_sim.v @@ -293,7 +293,6 @@ module fiftyfivenm_pll endmodule // max10_pll -//rih /* MAX10 MULT clearbox model */ (* blackbox *) module fiftyfivenm_mac_mult ( From 7647eb70a6906979a7001c47e9d02c7f64f0d1f5 Mon Sep 17 00:00:00 2001 From: Richard Herveille Date: Fri, 15 Mar 2024 01:48:22 +0100 Subject: [PATCH 6/7] removed commented out code --- techlibs/intel/synth_intel.cc | 9 --------- 1 file changed, 9 deletions(-) diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index 00e5766e9..11567ece9 100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -195,17 +195,8 @@ struct SynthIntelPass : public ScriptPass { run("read_verilog -sv -lib +/intel/common/altpll_bb.v"); run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt.c_str())); } -/* - if (flatten && check_label("flatten", "(unless -noflatten)")) { - run("proc"); - run("flatten"); - run("tribuf -logic"); - run("deminout"); - } -*/ if (check_label("coarse")) { -// run("synth -run coarse"); run("proc"); if (flatten || help_mode) run("flatten", "(skip if -noflatten)"); From 2893938355d786a0188753272cef5d95c3e10ccb Mon Sep 17 00:00:00 2001 From: Richard Herveille Date: Tue, 19 Mar 2024 01:31:36 +0100 Subject: [PATCH 7/7] Removed SystemVerilog module end label --- techlibs/intel/max10/cells_sim.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/techlibs/intel/max10/cells_sim.v b/techlibs/intel/max10/cells_sim.v index fe8c92b0a..b163aac40 100644 --- a/techlibs/intel/max10/cells_sim.v +++ b/techlibs/intel/max10/cells_sim.v @@ -322,7 +322,7 @@ module fiftyfivenm_mac_mult ( input aclr; input clk; input ena; -endmodule : fiftyfivenm_mac_mult +endmodule //fiftyfivenm_mac_mult module fiftyfivenm_mac_out ( dataa, @@ -342,4 +342,4 @@ module fiftyfivenm_mac_out ( input aclr; input clk; input ena; -endmodule : fiftyfivenm_mac_out +endmodule //fiftyfivenm_mac_out