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Revert "opt_clean: handle undriven and x-bit driven bits consistently"

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This reverts commit 8eb48fe446.
This commit is contained in:
Emil J. Tywoniak 2025-04-10 11:35:19 +02:00
parent ff88b7b2e8
commit 9f74e1bd2b
2 changed files with 4 additions and 32 deletions
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22
passes/opt/opt_clean.cc
View file

@ -31,20 +31,6 @@ PRIVATE_NAMESPACE_BEGIN
using RTLIL::id2cstr;
struct CleanerPool : SigPool
{
bool check_all_def(const RTLIL::SigSpec &sig) const
{
for (auto &bit : sig) {
if (bit.wire != NULL && bits.count(bit) == 0)
return false;
if (bit.wire == NULL && bit.data == RTLIL::State::Sx)
return false;
}
return true;
}
};
struct keep_cache_t
{
Design *design;
@ -404,7 +390,7 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool x_mode
// used signals pre-sigmapped
SigPool raw_used_signals;
// used signals sigmapped, ignoring drivers (we keep track of this to set `unused_bits`)
CleanerPool used_signals_nodrivers;
SigPool used_signals_nodrivers;
// gather the usage information for cells
for (auto &it : module->cells_) {
@ -520,14 +506,14 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool x_mode
module->connect(new_conn);
}
if (!used_signals_nodrivers.check_all_def(s2)) {
if (!used_signals_nodrivers.check_all(s2)) {
std::string unused_bits;
for (int i = 0; i < GetSize(s2); i++) {
if ((s2[i].wire == NULL) && (s2[i].data != RTLIL::State::Sx))
if (s2[i].wire == NULL)
continue;
if (!used_signals_nodrivers.check(s2[i])) {
if (!unused_bits.empty())
unused_bits += " ";
unused_bits += " ";
unused_bits += stringf("%d", i);
}
}

14
tests/opt/opt_clean_x.ys
View file

@ -1,14 +0,0 @@
read_verilog <<EOT
module alu(
);
wire [1:0] p1, p2;
assign p1 = 2'bx1;
assign p2[0] = 1'b1;
endmodule
EOT
proc
opt_clean
dump
select -assert-count 1 w:p1 a:unused_bits=1 %i
select -assert-count 1 w:p2 a:unused_bits=1 %i