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Consistent with xilinx

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This commit is contained in:
Eddie Hung 2019-06-03 09:23:43 -07:00
parent 2228cef62f
commit 9f44a71715
3 changed files with 4 additions and 4 deletions
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2
techlibs/ice40/cells_sim.v
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@ -145,7 +145,7 @@ endmodule
(* abc_box_id = 1, abc_flop, lib_whitebox *)
module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, (* abc_flop_d *) input D);
`ifndef ABC_MODEL
`ifndef _ABC
always @(posedge C)
Q <= D;
`else