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opt_merge: speedup

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This commit is contained in:
Eddie Hung 2020-03-10 16:13:44 -07:00
parent a0cc795e85
commit 9f30d7f843
3 changed files with 189 additions and 127 deletions
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64
tests/opt/opt_merge_keep.ys Normal file
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read_verilog -icells <<EOT
module top(input clk, i, output o, p);
(* keep *)
\$_DFF_P_ ffo (
.C(clk),
.D(i),
.Q(o)
);
\$_DFF_P_ ffp (
.C(clk),
.D(i),
.Q(p)
);
endmodule
EOT
opt_merge
select -assert-count 1 t:$_DFF_P_
select -assert-count 1 a:keep
design -reset
read_verilog -icells <<EOT
module top(input clk, i, output o, p);
\$_DFF_P_ ffo (
.C(clk),
.D(i),
.Q(o)
);
(* keep *)
\$_DFF_P_ ffp (
.C(clk),
.D(i),
.Q(p)
);
endmodule
EOT
opt_merge
select -assert-count 1 t:$_DFF_P_
select -assert-count 1 a:keep
design -reset
read_verilog -icells <<EOT
module top(input clk, i, output o, p);
(* keep *)
\$_DFF_P_ ffo (
.C(clk),
.D(i),
.Q(o)
);
(* keep *)
\$_DFF_P_ ffp (
.C(clk),
.D(i),
.Q(p)
);
endmodule
EOT
opt_merge
select -assert-count 2 t:$_DFF_P_
select -assert-count 2 a:keep