mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-03 21:09:12 +00:00
Code Activity

Further clean up passes/sat/freduce.cc.

Browse source 
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
This commit is contained in:
Alberto Gonzalez 2020-03-30 16:25:30 +00:00
parent 9a0cdc3835
commit 9f265dfd3f
No known key found for this signature in database
GPG key ID: 8395A8BA109708B2
1 changed files with 2 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

5
passes/sat/freduce.cc
View file

@ -828,9 +828,8 @@ struct FreducePass : public Pass {
extra_args(args, argidx, design);
int bitcount = 0;
for (auto module : design->modules()) {
if (design->selected(module))
bitcount += FreduceWorker(design, module).run();
for (auto module : design->selected_modules()) {
bitcount += FreduceWorker(design, module).run();
}
log("Rewired a total of %d signal bits.\n", bitcount);