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nexus: DSP inference support

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Signed-off-by: David Shah <dave@ds0.me>
This commit is contained in:
David Shah 2020-11-20 08:26:58 +00:00
parent 5b35d953f7
commit 9f241c9a42
4 changed files with 151 additions and 13 deletions
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46
tests/arch/nexus/mul.ys
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@ -1,4 +1,5 @@
read_verilog ../common/mul.v
chparam -set X_WIDTH 8 -set Y_WIDTH 8 -set A_WIDTH 16
hierarchy -top top
proc
@ -7,22 +8,43 @@ design -save read
equiv_opt -assert -map +/nexus/cells_sim.v synth_nexus
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 7 t:CCU2
select -assert-max 5 t:WIDEFN9
select -assert-max 62 t:LUT4
select -assert-count 1 t:MULT9X9
select -assert-none t:IB t:OB t:VLO t:VHI t:LUT4 t:CCU2 t:WIDEFN9 %% t:* %D
select -assert-none t:IB t:OB t:VLO t:VHI t:MULT9X9 %% t:* %D
design -load read
equiv_opt -assert -map +/nexus/cells_sim.v synth_nexus -abc9
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
design -reset
read_verilog ../common/mul.v
chparam -set X_WIDTH 16 -set Y_WIDTH 16 -set A_WIDTH 32
hierarchy -top top
proc
# equivalence checking is too slow here
synth_nexus
cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:MULT18X18
select -assert-none t:IB t:OB t:VLO t:VHI t:MULT18X18 %% t:* %D
stat
select -assert-count 7 t:CCU2
select -assert-max 12 t:WIDEFN9
select -assert-max 58 t:LUT4
design -reset
read_verilog ../common/mul.v
chparam -set X_WIDTH 32 -set Y_WIDTH 16 -set A_WIDTH 48
hierarchy -top top
proc
# equivalence checking is too slow here
synth_nexus
cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:MULT18X36
select -assert-none t:IB t:OB t:VLO t:VHI t:MULT18X36 %% t:* %D
select -assert-none t:IB t:OB t:VLO t:VHI t:LUT4 t:CCU2 t:WIDEFN9 %% t:* %D
design -reset
read_verilog ../common/mul.v
chparam -set X_WIDTH 32 -set Y_WIDTH 32 -set A_WIDTH 64
hierarchy -top top
proc
# equivalence checking is too slow here
synth_nexus
cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:MULT36X36
select -assert-none t:IB t:OB t:VLO t:VHI t:MULT36X36 %% t:* %D