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docs: work on example_synth
Split hardware mapping from `fifo.ys` into `fifo_map.ys`. Reduces size of `fifo.out` log and allows separate yosys calls in the makefile. Some tidy up and minor changes in `fifo.ys` for better discussion. Filled out note on `clean` (changed from `opt_clean`) and introduced `;;`. Highlighted `$memrd` and added a paragraph about it. More detail on the flatten and merging of `fifo_reader` block. Brief discussion on the changes from `$memrd` to `$memrd_v2`.
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5 changed files with 159 additions and 1774 deletions
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@ -149,25 +149,29 @@ each of these in more detail in :doc:`/using_yosys/synthesis/proc`.
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:doc:`/cmd/opt_expr`
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- by default called at the end of :cmd:ref:`proc`
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- can be disabled with ``-noopt``
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- done here for... reasons?
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Notice how in the top left of :ref:`addr_gen_proc` we have a floating wire,
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generated from the initial assignment of 0 to the ``addr`` wire. However, this
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initial assignment is not synthesizable, so this will need to be cleaned up
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before we can generate the physical hardware. We can do this now by calling
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:cmd:ref:`opt_clean`:
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:cmd:ref:`clean`:
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.. figure:: /_images/code_examples/fifo/addr_gen_clean.*
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:class: width-helper
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:name: addr_gen_clean
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``addr_gen`` module after :cmd:ref:`opt_clean`
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``addr_gen`` module after :cmd:ref:`clean`
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.. TODO:: more on opt_clean
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:doc:`/cmd/opt_clean`
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.. note::
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- :cmd:ref:`clean` for short, ``;;`` for even shorter
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- final command of :cmd:ref:`opt`
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- can run at any time
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:doc:`/cmd/clean` can also be called with two semicolons after any command,
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for example we could have called :yoscrypt:`proc;;` instead of
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:yoscrypt:`proc` and then :yoscrypt:`clean`. It is generally beneficial to
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run :cmd:ref:`clean` after each command as a quick way of removing
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disconnected parts of the circuit which have been left over. You may notice
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some scripts will end each line with ``;;``.
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.. todo:: consider a brief glossary for terms like adff
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@ -231,11 +235,15 @@ command only works with a single module, so you may need to call it with
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The highlighted ``fifo_reader`` block contains an instance of the
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:ref:`addr_gen_proc` that we looked at earlier. Notice how the type is shown as
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``$paramod\\addr_gen\\MAX_DATA=s32'...``. This is a "parametric module"; an
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instance of the ``addr_gen`` module with the ``MAX_DATA`` set to the given
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value.
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``$paramod\\addr_gen\\MAX_DATA=s32'...``. This is a "parametric module": an
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instance of the ``addr_gen`` module with the ``MAX_DATA`` parameter set to the
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given value.
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.. TODO:: comment on ``$memrd``
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The other highlighted block is a ``$memrd`` cell. At this stage of synthesis we
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don't yet know what type of memory is going to be implemented, but we *do* know
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that ``rdata <= data[raddr];`` could be implemented as a read from memory. Note
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that the ``$memrd`` cell here is asynchronous, with both the clock and enable
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signal undefined; shown with the ``1'x`` inputs.
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.. seealso:: Advanced usage docs for
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:doc:`/using_yosys/synthesis/proc`
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@ -261,7 +269,7 @@ optimizations between modules which would otherwise be missed. Let's run
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.. literalinclude:: /code_examples/fifo/fifo.out
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:language: doscon
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:start-at: yosys> flatten
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:end-before: yosys> show
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:end-before: yosys> select
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:name: flat_clean
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:caption: output of :yoscrypt:`flatten;;`
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@ -271,16 +279,24 @@ optimizations between modules which would otherwise be missed. Let's run
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``rdata`` output after :yoscrypt:`flatten;;`
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We can now see both :ref:`rdata_proc` and :ref:`addr_gen_proc` together. Note
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that in the :ref:`flat_clean` we see above has two separate calls: one to
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:cmd:ref:`flatten` and one to :cmd:ref:`clean`. In an interactive terminal the
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output of both commands will be combined into the single `yosys> flatten;;`
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output.
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.. role:: yoterm(code)
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:language: doscon
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Depending on the target architecture, we might also see commands such as
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:cmd:ref:`tribuf` with the ``-logic`` option and :cmd:ref:`deminout`. These
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remove tristate and inout constructs respectively, replacing them with logic
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suitable for mapping to an FPGA.
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The pieces have moved around a bit, but we can see :ref:`addr_gen_proc` from
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earlier has replaced the ``fifo_reader`` block in :ref:`rdata_proc`. We can
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also see that the ``addr`` output has been renamed to ``fifo_reader.addr`` and
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merged with the ``raddr`` wire feeding into the ``$memrd`` cell. This wire
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merging happened during the call to :cmd:ref:`clean` which we can see in the
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:ref:`flat_clean`. Note that in an interactive terminal the outputs of
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:cmd:ref:`flatten` and :cmd:ref:`clean` will be combined into a single
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:yoterm:`yosys> flatten;;` output.
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Depending on the target architecture, this stage of synthesis might also see
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commands such as :cmd:ref:`tribuf` with the ``-logic`` option and
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:cmd:ref:`deminout`. These remove tristate and inout constructs respectively,
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replacing them with logic suitable for mapping to an FPGA. Since we do not have
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any such constructs in our example running these commands does not change our
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design.
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The coarse-grain representation
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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@ -314,18 +330,18 @@ In the iCE40 flow, we start with the following commands:
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:caption: ``coarse`` section (part 1)
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:name: synth_coarse1
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The first few commands are relatively straightforward, and we've already come
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across :cmd:ref:`opt_clean` and :cmd:ref:`opt_expr`. The :cmd:ref:`check` pass
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identifies a few obvious problems which will cause errors later. Calling it
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here lets us fail faster rather than wasting time on something we know is
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We've already come across :cmd:ref:`opt_expr`, and :cmd:ref:`opt_clean` is the
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same as :cmd:ref:`clean` but with more verbose output. The :cmd:ref:`check`
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pass identifies a few obvious problems which will cause errors later. Calling
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it here lets us fail faster rather than wasting time on something we know is
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impossible.
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Next up is :yoscrypt:`opt -nodffe -nosdff` performing a set of simple
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optimizations on the design. This command also ensures that only a specific
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subset of FF types are included, in preparation for the next command:
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:doc:`/cmd/fsm`. Both :cmd:ref:`opt` and :cmd:ref:`fsm` are macro commands
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which are explored in more detail in :doc:`/using_yosys/synthesis/fsm` and
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:doc:`/using_yosys/synthesis/opt` respectively.
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which are explored in more detail in :doc:`/using_yosys/synthesis/opt` and
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:doc:`/using_yosys/synthesis/fsm` respectively.
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Up until now, the data path for ``rdata`` has remained the same since
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:ref:`rdata_flat`. However the next call to :cmd:ref:`opt` does cause a change.
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``rdata`` output after :cmd:ref:`memory_dff`
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As the title suggests, :cmd:ref:`memory_dff` has merged the output ``$dff`` into
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the ``$memrd`` cell and converted it to a ``$memrd_v2`` (highlighted).
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the ``$memrd`` cell and converted it to a ``$memrd_v2`` (highlighted). This has
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also connected the ``CLK`` port to the ``clk`` input as it is now a synchronous
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memory read with appropriate enable (``EN=1'1``) and reset (``ARST=1'0`` and
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``SRST=1'0``) inputs.
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.. seealso:: Advanced usage docs for
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