mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-11 08:33:26 +00:00
Code Activity

docs: work on example_synth

Browse source 
Split hardware mapping from `fifo.ys` into `fifo_map.ys`.  Reduces size of `fifo.out` log and allows separate yosys calls in the makefile.

Some tidy up and minor changes in `fifo.ys` for better discussion.
Filled out note on `clean` (changed from `opt_clean`) and introduced `;;`.
Highlighted `$memrd` and added a paragraph about it.
More detail on the flatten and merging of `fifo_reader` block.
Brief discussion on the changes from `$memrd` to `$memrd_v2`.
This commit is contained in:
Krystine Sherwin 2024-01-03 11:47:33 +13:00
parent 50d8c1b258
commit 9f1c445fbf
No known key found for this signature in database
5 changed files with 159 additions and 1774 deletions
Download patch file Download diff file Expand all files Collapse all files

58
docs/source/code_examples/fifo/fifo.ys
View file

@ -18,7 +18,7 @@ select -set new_cells t:$mux t:*dff
show -color maroon3 @new_cells -notitle -format dot -prefix addr_gen_proc
# ========================================================
opt_clean
clean
show -notitle -format dot -prefix addr_gen_clean
# ========================================================
@ -26,12 +26,15 @@ design -reset
read_verilog fifo.v
hierarchy -check -top fifo
proc
show -color maroon3 c:fifo_reader -notitle -format dot -prefix rdata_proc o:rdata %ci*
select -set new_cells t:$memrd
show -color maroon3 c:fifo_reader -color cornflowerblue @new_cells -notitle -format dot -prefix rdata_proc o:rdata %ci*
# ========================================================
flatten;;
show -notitle -format dot -prefix rdata_flat o:rdata %ci*
select -set rdata_path o:rdata %ci*
select -set new_cells @rdata_path o:rdata %ci3 %d i:* %d
show -color maroon3 @new_cells -notitle -format dot -prefix rdata_flat @rdata_path
# ========================================================
@ -53,54 +56,7 @@ show -color maroon3 @new_cells -notitle -format dot -prefix rdata_alumacc o:rdat
# ========================================================
design -reset
read_verilog fifo.v
synth_ice40 -top fifo -run begin:map_ram
memory -nomap
select -set new_cells t:$mem_v2
select -set rdata_path @new_cells %ci*:-$mem_v2[WR_DATA,WR_ADDR,WR_EN] @new_cells %co* %%
show -color maroon3 @new_cells -notitle -format dot -prefix rdata_coarse @rdata_path
# turn command echoes off to avoid randomly generated abc file names
echo off
# ========================================================
synth_ice40 -top fifo -run map_ram:map_ffram
select -set new_cells t:SB_RAM40_4K
select -set rdata_path @new_cells %ci*:-SB_RAM40_4K[WDATA,WADDR,WE] @new_cells %co* %%
show -color maroon3 @new_cells -notitle -format dot -prefix rdata_map_ram @rdata_path
# ========================================================
synth_ice40 -top fifo -run map_ffram:map_gates
select -set new_cells t:SB_RAM40_4K
select -set rdata_path @new_cells %ci*:-SB_RAM40_4K[WDATA,WADDR,WE] @new_cells %co* %%
show -color maroon3 @new_cells -notitle -format dot -prefix rdata_map_ffram @rdata_path
# ========================================================
synth_ice40 -top fifo -run map_gates:map_ffs
select -set new_cells t:SB_RAM40_4K
select -set rdata_path @new_cells %ci*:-SB_RAM40_4K[WDATA,WADDR,WE] @new_cells %co* %%
show -color maroon3 @new_cells -notitle -format dot -prefix rdata_map_gates @rdata_path
# ========================================================
synth_ice40 -top fifo -run map_ffs:map_luts
select -set new_cells t:SB_RAM40_4K
select -set rdata_path @new_cells %ci*:-SB_RAM40_4K[WDATA,WADDR,WE] @new_cells %co* %%
show -color maroon3 @new_cells -notitle -format dot -prefix rdata_map_ffs @rdata_path
# ========================================================
synth_ice40 -top fifo -run map_luts:map_cells
select -set new_cells t:SB_RAM40_4K
select -set rdata_path @new_cells %ci*:-SB_RAM40_4K[WDATA,WADDR,WE] @new_cells %co* %%
show -color maroon3 @new_cells -notitle -format dot -prefix rdata_map_luts @rdata_path
# ========================================================
synth_ice40 -top fifo -run map_cells:
select -set new_cells t:SB_RAM40_4K
select -set rdata_path @new_cells %ci*:-SB_RAM40_4K[WDATA,WADDR,WE] @new_cells %co* %%
show -color maroon3 @new_cells -notitle -format dot -prefix rdata_map_cells @rdata_path