From 9a14ab8d98cdaaf2a680ad744aeb11db2226c592 Mon Sep 17 00:00:00 2001
From: Anhijkt <mihail.ershov.zp@gmail.com>
Date: Fri, 28 Feb 2025 13:51:22 +0200
Subject: [PATCH 1/3] splitcells: Fix the assertion bug caused by out-of-bound
 offset

---
 passes/cmds/splitcells.cc | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/passes/cmds/splitcells.cc b/passes/cmds/splitcells.cc
index 074bf0f64..e3d509564 100644
--- a/passes/cmds/splitcells.cc
+++ b/passes/cmds/splitcells.cc
@@ -103,8 +103,7 @@ struct SplitcellsWorker
 
 				auto slice_signal = [&](SigSpec old_sig) -> SigSpec {
 					SigSpec new_sig;
-					for (int i = 0; i < GetSize(old_sig); i += GetSize(outsig)) {
-						int offset = i+slice_lsb;
+					for (int offset = slice_lsb; offset <= GetSize(old_sig); offset += GetSize(outsig)) {
 						int length = std::min(GetSize(old_sig)-offset, slice_msb-slice_lsb+1);
 						new_sig.append(old_sig.extract(offset, length));
 					}

From de032d2e2ac766df596ab4a11ecf14175b9c8fb4 Mon Sep 17 00:00:00 2001
From: Anhijkt <mihail.ershov.zp@gmail.com>
Date: Fri, 28 Feb 2025 23:16:04 +0200
Subject: [PATCH 2/3] splitcells: change for-loop condition

---
 passes/cmds/splitcells.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/passes/cmds/splitcells.cc b/passes/cmds/splitcells.cc
index e3d509564..d2063a0c8 100644
--- a/passes/cmds/splitcells.cc
+++ b/passes/cmds/splitcells.cc
@@ -103,7 +103,7 @@ struct SplitcellsWorker
 
 				auto slice_signal = [&](SigSpec old_sig) -> SigSpec {
 					SigSpec new_sig;
-					for (int offset = slice_lsb; offset <= GetSize(old_sig); offset += GetSize(outsig)) {
+					for (int offset = slice_lsb; offset < GetSize(old_sig); offset += GetSize(outsig)) {
 						int length = std::min(GetSize(old_sig)-offset, slice_msb-slice_lsb+1);
 						new_sig.append(old_sig.extract(offset, length));
 					}

From be3dfdc5ad01019d7f843f1acb9a1640316e60ab Mon Sep 17 00:00:00 2001
From: Anhijkt <mihail.ershov.zp@gmail.com>
Date: Mon, 10 Mar 2025 19:41:22 +0200
Subject: [PATCH 3/3] splitcells: add tests

---
 tests/various/bug4909.ys | 44 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)
 create mode 100644 tests/various/bug4909.ys

diff --git a/tests/various/bug4909.ys b/tests/various/bug4909.ys
new file mode 100644
index 000000000..bf8cfb45b
--- /dev/null
+++ b/tests/various/bug4909.ys
@@ -0,0 +1,44 @@
+read_rtlil << EOF
+autoidx 20
+attribute \src "3510.v:2.1-26.10"
+attribute \cells_not_processed 1
+attribute \tamara_triplicate 1
+module \top
+  attribute \src "3510.v:14.3-17.8"
+  wire width 4 $0\reg5[3:0]
+  attribute $bugpoint 1
+  wire width 4 $auto$bugpoint.cc:258:simplify_something$12
+  wire $delete_wire$14
+  attribute \src "3510.v:13.19-13.59"
+  wire width 4 $xnor$3510.v:13$1_Y
+  attribute \src "3510.v:11.23-11.27"
+  wire width 4 \reg5
+  attribute \src "3510.v:8.24-8.29"
+  wire width 3 \wire4
+  attribute \src "3510.v:3.33-3.34"
+  wire width 12 output 1 \y
+  attribute \src "3510.v:13.19-13.59"
+  cell $xnor $xnor$3510.v:13$1
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 3
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 4
+    parameter \Y_WIDTH 4
+    connect \A 3'x
+    connect \B $auto$bugpoint.cc:258:simplify_something$12
+    connect \Y $xnor$3510.v:13$1_Y
+  end
+  attribute \src "3510.v:14.3-17.8"
+  process $proc$3510.v:14$2
+    assign $0\reg5[3:0] { \wire4 [2] \wire4 }
+    sync posedge $delete_wire$14
+      update \reg5 $0\reg5[3:0]
+  end
+  connect \y [4:0] { \reg5 1'0 }
+  connect \wire4 $xnor$3510.v:13$1_Y [2:0]
+end
+EOF
+
+prep
+splitcells
+