mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-04 05:19:11 +00:00
Code Activity

added optimizations for single-bit $eq/$ne with constant input to opt_const

Browse source
This commit is contained in:
Clifford Wolf 2013-03-19 13:33:33 +01:00
parent d8a7fa6b67
commit 9f10acb840
1 changed files with 25 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

25
passes/opt/opt_const.cc
View file

@ -174,6 +174,31 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module)
}
}
if ((cell->type == "$eq" || cell->type == "$ne") && cell->parameters["\\Y_WIDTH"].as_int() == 1 &&
cell->parameters["\\A_WIDTH"].as_int() == 1 && cell->parameters["\\B_WIDTH"].as_int() == 1)
{
RTLIL::SigSpec a = assign_map(cell->connections["\\A"]);
RTLIL::SigSpec b = assign_map(cell->connections["\\B"]);
if (a.is_fully_const()) {
RTLIL::SigSpec tmp = a;
a = b, b = tmp;
}
if (b.is_fully_const()) {
if (b.as_bool() == (cell->type == "$eq")) {
RTLIL::SigSpec input = b;
ACTION_DO("\\Y", cell->connections["\\A"]);
} else {
cell->type = "$not";
cell->parameters.erase("\\B_WIDTH");
cell->parameters.erase("\\B_SIGNED");
cell->connections.erase("\\B");
}
goto next_cell;
}
}
#define FOLD_1ARG_CELL(_t) \
if (cell->type == "$" #_t) { \
RTLIL::SigSpec a = cell->connections["\\A"]; \