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gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.

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whitequark 2018-12-05 04:50:38 +00:00
parent 12596b5003
commit 9ef078848a
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tests/lut/map_mux.v Normal file
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module top(...);
input a, b, s;
output y;
assign y = s?a:b;
endmodule